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| author | Bin Meng <bmeng.cn@gmail.com> | 2018-08-10 02:39:37 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2018-08-20 13:52:49 +0800 |
| commit | 864915561b3273a4f8894804146d6739e8e49ab2 (patch) | |
| tree | 3ad436482e133d4e9991f9fd8e970e9bf4c21d80 /arch/x86/dts/coreboot.dts | |
| parent | 165db7c426f1946376c3643fd635afd6b167e3ee (diff) | |
| download | u-boot-864915561b3273a4f8894804146d6739e8e49ab2.zip u-boot-864915561b3273a4f8894804146d6739e8e49ab2.tar.gz u-boot-864915561b3273a4f8894804146d6739e8e49ab2.tar.bz2 | |
x86: coreboot: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Diffstat (limited to 'arch/x86/dts/coreboot.dts')
| -rw-r--r-- | arch/x86/dts/coreboot.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index a94f781..e212f3d 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; |