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authorSimon Glass <sjg@chromium.org>2020-11-04 09:57:15 -0700
committerBin Meng <bmeng.cn@gmail.com>2020-11-05 14:58:45 +0800
commit6571d873159789ee7caa571eafa5fa641005971c (patch)
treebcb0f59b372597fae7916946cd6be44424a435bf /arch/x86/cpu/intel_common/cpu.c
parent1779b8a96a32706dc8e2e71187889b38d9822443 (diff)
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x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/intel_common/cpu.c')
-rw-r--r--arch/x86/cpu/intel_common/cpu.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 39aa0f6..a51bf86 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -306,3 +306,22 @@ int cpu_get_cores_per_package(void)
return cores;
}
+
+void cpu_mca_configure(void)
+{
+ msr_t msr;
+ int i;
+ int num_banks;
+
+ msr = msr_read(MSR_IA32_MCG_CAP);
+ num_banks = msr.lo & 0xff;
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < num_banks; i++) {
+ /* Clear the machine check status */
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
+ /* Initialise machine checks */
+ msr_write(MSR_IA32_MC0_CTL + i * 4,
+ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
+ }
+}