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| author | Simon Glass <sjg@chromium.org> | 2014-11-14 18:18:43 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-25 06:34:02 -0700 |
| commit | 18739e2ccc66e13dba10a7cb4578910daf455f01 (patch) | |
| tree | 3b80e9bd185f69041ad4cd1686d1bf95c08762f4 /arch/x86/cpu/Makefile | |
| parent | a6d4c453069303c3d1a499d2282f423b35c8f3b0 (diff) | |
| download | u-boot-18739e2ccc66e13dba10a7cb4578910daf455f01.zip u-boot-18739e2ccc66e13dba10a7cb4578910daf455f01.tar.gz u-boot-18739e2ccc66e13dba10a7cb4578910daf455f01.tar.bz2 | |
x86: Add Intel speedstep and turbo mode code
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/Makefile')
| -rw-r--r-- | arch/x86/cpu/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 818969f..3839262 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_PCI) += pci.o +obj-y += turbo.o |