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authorPhil Edworthy <PHIL.EDWORTHY@renesas.com>2011-06-01 07:35:13 +0100
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2011-08-22 13:16:08 +0900
commit7fbeb6422d9fb32063c8357fcdee99f0088a1a7f (patch)
tree38ec79a5bd9f7c4784bc6e518b848bc95e894785 /arch/sh
parentfa82f871c8dbc9a15e8dc274b3f99dd5fa0da458 (diff)
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sh: Add Renesas rsk7264 board
The rsk7264 (also know as rsk2+sh7264) is an SH2A based board with 64MB NAND flash and 64MB SDRAM. It is very similar to the rsk7203 board. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/cpu/sh2/cpu.c7
-rw-r--r--arch/sh/include/asm/cpu_sh2.h2
-rw-r--r--arch/sh/include/asm/cpu_sh7264.h41
3 files changed, 50 insertions, 0 deletions
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index 6bbedd9..fff25ac 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -33,6 +33,9 @@
#define scif0_enable() do {\
writeb(readb(STBCR4) & ~0x80, STBCR4);\
} while (0)
+#define scif3_enable() do {\
+ writeb(readb(STBCR4) & ~0x10, STBCR4);\
+ } while (0)
int checkcpu(void)
{
@@ -47,7 +50,11 @@ int checkcpu(void)
int cpu_init(void)
{
/* SCIF enable */
+#if defined(CONFIG_CONS_SCIF3)
+ scif3_enable();
+#else
scif0_enable();
+#endif
/* CMT clock enable */
cmt_clock_enable() ;
return 0;
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index 8bc9bc6..767e189 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -33,6 +33,8 @@
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
+#elif defined(CONFIG_CPU_SH7264)
+# include <asm/cpu_sh7264.h>
#else
# error "Unknown SH2 variant"
#endif
diff --git a/arch/sh/include/asm/cpu_sh7264.h b/arch/sh/include/asm/cpu_sh7264.h
new file mode 100644
index 0000000..a4a4d51
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7264.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CPU_SH7264_H_
+#define _ASM_CPU_SH7264_H_
+
+/* Cache */
+#define CCR1 0xFFFC1000
+#define CCR CCR1
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PETCR 0xA4050106
+
+/* Port Data Registers */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+
+/* BSC */
+
+/* SDRAM controller */
+
+/* SCIF */
+#define SCSMR_3 0xFFFE9800
+#define SCIF3_BASE SCSMR_3
+
+/* Timer(CMT) */
+#define CMSTR 0xFFFEC000
+#define CMCSR_0 0xFFFEC002
+#define CMCNT_0 0xFFFEC004
+#define CMCOR_0 0xFFFEC006
+#define CMCSR_1 0xFFFEC008
+#define CMCNT_1 0xFFFEC00A
+#define CMCOR_1 0xFFFEC00C
+
+/* On chip oscillator circuits */
+#define FRQCR 0xA415FF80
+#define WTCNT 0xA415FF84
+#define WTCSR 0xA415FF86
+
+#endif /* _ASM_CPU_SH7264_H_ */