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| author | Alex Marginean <alexm.osslist@gmail.com> | 2019-06-07 11:24:24 +0300 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2019-07-10 16:52:58 -0600 |
| commit | 21ebbafde8dbbc5903a302ba0c126ff2ac1423c8 (patch) | |
| tree | 7619308eb2da99597e30de33845f4df4288c5d54 /arch/sandbox | |
| parent | 0b143d8ab2b84219552d652e46619360a38888d1 (diff) | |
| download | u-boot-21ebbafde8dbbc5903a302ba0c126ff2ac1423c8.zip u-boot-21ebbafde8dbbc5903a302ba0c126ff2ac1423c8.tar.gz u-boot-21ebbafde8dbbc5903a302ba0c126ff2ac1423c8.tar.bz2 | |
test: dm: Add a test for PCI Enhanced Allocation
This test is built on top of the existing swap_case driver. It adds EA
capability structure support to swap_case and uses that to map BARs.
BAR1 works as it used to, swapping upper/lower case. BARs 2,4 map to a
couple of magic values.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/sandbox')
| -rw-r--r-- | arch/sandbox/dts/test.dts | 8 | ||||
| -rw-r--r-- | arch/sandbox/include/asm/test.h | 13 |
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index c328258..ee0f631 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -446,6 +446,14 @@ compatible = "sandbox,swap-case"; }; }; + pci@1,0 { + compatible = "pci-generic"; + reg = <0x0800 0 0 0 0>; + emul@0,0 { + compatible = "sandbox,swap-case"; + use-ea; + }; + }; pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index e956a05..32125f3 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -19,6 +19,7 @@ #define PCI_CAP_ID_PM_OFFSET 0x50 #define PCI_CAP_ID_EXP_OFFSET 0x60 #define PCI_CAP_ID_MSIX_OFFSET 0x70 +#define PCI_CAP_ID_EA_OFFSET 0x80 #define PCI_EXT_CAP_ID_ERR_OFFSET 0x100 #define PCI_EXT_CAP_ID_VC_OFFSET 0x200 @@ -30,6 +31,18 @@ #define SANDBOX_CLK_RATE 32768 +/* Macros used to test PCI EA capability structure */ +#define PCI_CAP_EA_BASE_LO0 0x00100000 +#define PCI_CAP_EA_BASE_LO1 0x00110000 +#define PCI_CAP_EA_BASE_LO2 0x00120000 +#define PCI_CAP_EA_BASE_LO4 0x00140000 +#define PCI_CAP_EA_BASE_HI2 0x00020000ULL +#define PCI_CAP_EA_BASE_HI4 0x00040000ULL +#define PCI_CAP_EA_SIZE_LO 0x0000ffff +#define PCI_CAP_EA_SIZE_HI 0x00000010ULL +#define PCI_EA_BAR2_MAGIC 0x72727272 +#define PCI_EA_BAR4_MAGIC 0x74747474 + /* System controller driver data */ enum { SYSCON0 = 32, |