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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2023-10-31 14:55:52 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-02 16:22:06 +0800 |
| commit | ceec977ba1a994df423cd8558f72d6582e63da08 (patch) | |
| tree | 5a776fd8812046f5bd06ecc8163551d0dab070f4 /arch/riscv | |
| parent | 9757cae991669f9a3d2b981b77231ee891d0597d (diff) | |
| download | u-boot-ceec977ba1a994df423cd8558f72d6582e63da08.zip u-boot-ceec977ba1a994df423cd8558f72d6582e63da08.tar.gz u-boot-ceec977ba1a994df423cd8558f72d6582e63da08.tar.bz2 | |
rng: Provide a RNG based on the RISC-V Zkr ISA extension
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.
A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions