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authorBin Meng <bin.meng@windriver.com>2021-01-31 20:36:04 +0800
committerSimon Glass <sjg@chromium.org>2021-02-03 03:38:41 -0700
commit86c915628d582a36029ff1f6c4443b6e81e0d51f (patch)
tree7dd83c74c724239c300368f848944685113f4f97 /arch/riscv
parentd17e9d2558ecbc2d6486555e6717396356b1f4e1 (diff)
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riscv: Change phys_addr_t and phys_size_t to 64-bit
phys_addr_t and phys_size_t are currently defined as `unsigned long`, but RV32 supports 34-bit physical address, hence both phys_addr_t and phys_size_t should be defined to 64-bit using `unsigned long long`. Signed-off-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/include/asm/types.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index b800b2d..49f7a5d 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -35,8 +35,8 @@ typedef u64 dma_addr_t;
typedef u32 dma_addr_t;
#endif
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
#endif /* __KERNEL__ */