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| author | Bin Meng <bmeng@tinylab.org> | 2023-04-13 14:20:01 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-04-20 20:45:08 +0800 |
| commit | 0b1a3a22de2624f6293c6b3dd42cff7cf1c99afd (patch) | |
| tree | ccc943e5acefeb4ac66b1439e45bdd3b95bfec7b /arch/riscv | |
| parent | 883f553e6ba510d4d4ab7d645ff46bc999752e79 (diff) | |
| download | u-boot-0b1a3a22de2624f6293c6b3dd42cff7cf1c99afd.zip u-boot-0b1a3a22de2624f6293c6b3dd42cff7cf1c99afd.tar.gz u-boot-0b1a3a22de2624f6293c6b3dd42cff7cf1c99afd.tar.bz2 | |
riscv: Optimize loading relocation type
't5' already contains relocation type so don't bother reloading it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 3c8344c..879bdc1 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -323,7 +323,6 @@ fix_rela_dyn: add t4, t4, t6 9: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ andi t5, t5, 0xFF /* t5 <--- relocation type */ li t3, RELOC_TYPE |