aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv
diff options
context:
space:
mode:
authorHeinrich Schuchardt <xypron.glpk@gmx.de>2020-08-03 23:09:49 +0200
committerAndes <uboot@andestech.com>2020-08-14 14:39:14 +0800
commit6a43e3a16743e5fc5b765bf897691b630e3e1edb (patch)
tree3acbff314920cf764690f4cb2ff0db575a6ee25c /arch/riscv
parent023dba13668756e54ac4522543d91840f8f34db5 (diff)
downloadu-boot-6a43e3a16743e5fc5b765bf897691b630e3e1edb.zip
u-boot-6a43e3a16743e5fc5b765bf897691b630e3e1edb.tar.gz
u-boot-6a43e3a16743e5fc5b765bf897691b630e3e1edb.tar.bz2
riscv: sifive: fu540: redundant initialization
We should not initialize a variable if the value is overwritten before being read. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/cpu/fu540/cache.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
index 9ee364b..54de142 100644
--- a/arch/riscv/cpu/fu540/cache.c
+++ b/arch/riscv/cpu/fu540/cache.c
@@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
- int node = (-FDT_ERR_NOTFOUND);
+ int node;
fdt_addr_t base;
u32 config;
u32 ways;