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authorSean Anderson <seanga2@gmail.com>2020-09-28 10:52:25 -0400
committerAndes <uboot@andestech.com>2020-09-30 08:54:46 +0800
commit15943bb558d2fef6ae6d2713e252db17754d207d (patch)
tree9345b19fd7184cb7824e6dbb7eb439d16c054dfd /arch/riscv
parente86463f8e3a5006b43985c474ac74d0caabd0fd4 (diff)
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riscv: Clean up initialization in Andes PLIC
This merges the PLIC initialization code from two functions into one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/lib/andes_plic.c58
1 files changed, 25 insertions, 33 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index c2a8fe4..267d6a1 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -41,53 +41,45 @@ static int enable_ipi(int hart)
return 0;
}
-static int init_plic(void)
+int riscv_init_ipi(void)
{
- struct udevice *dev;
- ofnode node;
int ret;
+ long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+ ofnode node;
+ struct udevice *dev;
u32 reg;
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ gd->arch.plic = base;
+
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
return ret;
+ else if (!dev)
+ return -ENODEV;
- if (dev) {
- ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
- const char *device_type;
-
- device_type = ofnode_read_string(node, "device_type");
- if (!device_type)
- continue;
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
- if (strcmp(device_type, "cpu"))
- continue;
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
- /* skip if hart is marked as not available */
- if (!ofnode_is_available(node))
- continue;
+ if (strcmp(device_type, "cpu"))
+ continue;
- /* read hart ID of CPU */
- ret = ofnode_read_u32(node, "reg", &reg);
- if (ret == 0)
- enable_ipi(reg);
- }
+ /* skip if hart is marked as not available */
+ if (!ofnode_is_available(node))
+ continue;
- return 0;
+ /* read hart ID of CPU */
+ ret = ofnode_read_u32(node, "reg", &reg);
+ if (ret == 0)
+ enable_ipi(reg);
}
- return -ENODEV;
-}
-
-int riscv_init_ipi(void)
-{
- long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
-
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- gd->arch.plic = ret;
-
- return init_plic();
+ return 0;
}
int riscv_send_ipi(int hart)