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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2022-10-14 15:00:18 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-10-20 15:23:41 +0800 |
| commit | bdb238355c37ac175520577fd2355f01db29714b (patch) | |
| tree | 344966a2edb09c50e5bc218014d0790104dbe242 /arch/riscv/lib | |
| parent | cb052d771200b15717eeb68f185cf7caa2dcfea0 (diff) | |
| download | u-boot-bdb238355c37ac175520577fd2355f01db29714b.zip u-boot-bdb238355c37ac175520577fd2355f01db29714b.tar.gz u-boot-bdb238355c37ac175520577fd2355f01db29714b.tar.bz2 | |
riscv: andes_plic.c: use modified IPI scheme
The IPI scheme in OpenSBI has been updated to support 8-core AE350
platform, the plicsw configuration needs to be modified accordingly.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/andes_plic.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 6851475..1eabcac 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,8 +27,8 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; @@ -36,8 +36,9 @@ static int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; } |