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| author | Rick Chen <rick@andestech.com> | 2018-11-07 09:34:06 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-11-26 13:58:01 +0800 |
| commit | 52923c6db7f00e0197ec894c8c1bb8a7681974bb (patch) | |
| tree | 903fe89d39120e2cfaf553f8cdfe0aeb2b5b106c /arch/riscv/include | |
| parent | bae2d72507abe8e17bdac30027c8748d22721024 (diff) | |
| download | u-boot-52923c6db7f00e0197ec894c8c1bb8a7681974bb.zip u-boot-52923c6db7f00e0197ec894c8c1bb8a7681974bb.tar.gz u-boot-52923c6db7f00e0197ec894c8c1bb8a7681974bb.tar.bz2 | |
riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ca83dd6..ec8fe20 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,6 +7,9 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +/* cache */ +void cache_flush(void); + /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * We use that value for aligning DMA buffers unless the board config has |