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| author | Sagar Shrikant Kadam <sagar.kadam@sifive.com> | 2020-07-29 02:36:12 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-08-04 09:19:41 +0800 |
| commit | ea4e9570ebed70c785e0076c65c5490cbd2c947b (patch) | |
| tree | 40ac9ae7f94dab82447e357835e70d2247bd748f /arch/riscv/dts | |
| parent | d2e43986373b75cdc00332106e6cca8bb5db452c (diff) | |
| download | u-boot-ea4e9570ebed70c785e0076c65c5490cbd2c947b.zip u-boot-ea4e9570ebed70c785e0076c65c5490cbd2c947b.tar.gz u-boot-ea4e9570ebed70c785e0076c65c5490cbd2c947b.tar.bz2 | |
fu540: dtsi: add reset producer and consumer entries
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv/dts')
| -rw-r--r-- | arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index afdb4f4..5302677 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 SiFive, Inc */ +#include <dt-bindings/reset/sifive-fu540-prci.h> + / { cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; @@ -59,6 +61,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc@100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 |