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authorThomas Skibo <thomas-git@skibo.net>2021-11-24 14:32:09 -0800
committerLeo Yu-Chi Liang <ycliang@andestech.com>2021-12-02 16:43:56 +0800
commit6a863894ad53b2d0e6c6d47ad105850053757fec (patch)
tree6b3c388872fce40712b633a34f8beab04e3d76e1 /arch/riscv/dts
parentffb78a7c71d555be31c8f8f2bb0fcc2fcfe3892e (diff)
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riscv: Support booting SiFive Unmatched from SPI.
Configure SPI flash devices into SPL. Add SPI boot option to spl.c. Document how to format flash for booting. Signed-off-by: Thomas Skibo <thomas-git@skibo.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/dts')
-rw-r--r--arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
index c5475aa..1ee8ab1 100644
--- a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
@@ -16,6 +16,10 @@
u-boot,dm-spl;
};
+ config {
+ u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */
+ };
+
hfclk {
u-boot,dm-spl;
};
@@ -30,6 +34,13 @@
clocks = <&rtcclk>;
};
+&qspi0 {
+ u-boot,dm-spl;
+ flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
&spi0 {
mmc@0 {
u-boot,dm-spl;