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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-02-06 16:10:48 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-17 19:07:48 +0800 |
| commit | c1b88196807e1dd797aea6cc7ddb0dce02b4e898 (patch) | |
| tree | ec1bb1c7873da8c127ef423a049291c4d737d93b /arch/riscv/dts | |
| parent | d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5 (diff) | |
| download | u-boot-c1b88196807e1dd797aea6cc7ddb0dce02b4e898.zip u-boot-c1b88196807e1dd797aea6cc7ddb0dce02b4e898.tar.gz u-boot-c1b88196807e1dd797aea6cc7ddb0dce02b4e898.tar.bz2 | |
riscv: ae350: dts: Update L2 cache compatible string
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/dts')
| -rw-r--r-- | arch/riscv/dts/ae350_32.dts | 2 | ||||
| -rw-r--r-- | arch/riscv/dts/ae350_64.dts | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 96ef8bd..61af6d5 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0xe0500000 0x40000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index cddbaec..8c7db29 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; |