diff options
| author | Tom Rini <trini@konsulko.com> | 2019-08-26 09:50:46 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-08-26 09:50:46 -0400 |
| commit | 7a4b0bc5fe70225ae3595ba81d1473c06fd6b83b (patch) | |
| tree | 08de46c2eb44560654871f78380d4363efdce5ec /arch/riscv/Kconfig | |
| parent | 6f9656d726235b4cbb4f469a82c30e5006a75b53 (diff) | |
| parent | 44016bc59870c8816fe2cd4721dc5ff11038dd98 (diff) | |
| download | u-boot-7a4b0bc5fe70225ae3595ba81d1473c06fd6b83b.zip u-boot-7a4b0bc5fe70225ae3595ba81d1473c06fd6b83b.tar.gz u-boot-7a4b0bc5fe70225ae3595ba81d1473c06fd6b83b.tar.bz2 | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.
- Fix qemu kconfig build warning.
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 36 |
1 files changed, 31 insertions, 5 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8cfc7d0..01975d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,6 +113,23 @@ config RISCV_SMODE endchoice +choice + prompt "SPL Run Mode" + default SPL_RISCV_MMODE + depends on SPL + +config SPL_RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot SPL for RISC-V M-Mode. + +config SPL_RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot SPL for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -132,34 +149,40 @@ config 64BIT config SIFIVE_CLINT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config ANDES_PLIC bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. config ANDES_PLMT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. config RISCV_RDTIME bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE help The provides the riscv_get_time() API that is implemented using the standard rdtime instruction. This is the case for S-mode U-Boot, and @@ -189,7 +212,7 @@ config NR_CPUS config SBI_IPI bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP config XIP @@ -203,4 +226,7 @@ config STACK_SIZE_SHIFT int default 13 +config SPL_LDSCRIPT + default "arch/riscv/cpu/u-boot-spl.lds" + endmenu |