Merge branch 'next'

Signed-off-by: Tom Rini <trini@konsulko.com>

19 files changed, 64 insertions, 1768 deletions

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index bcd8375..2ebf8fc 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -1,6 +1,9 @@
 menu "mpc83xx CPU"
 	depends on MPC83xx
 
+config E300
+	def_bool y
+
 config SYS_CPU
 	default "mpc83xx"
 
@@ -200,7 +203,6 @@ config FSL_ELBC
 
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
-source "board/keymile/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 3393ad5..33b2151 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -51,9 +51,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 		 REVID_MAJOR(spridr) >= 2)
 		fdt_fixup_crypto_node(blob, 0x0204);
 
-#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
-    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
-    defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
 #ifdef CONFIG_ARCH_MPC8313
 	/*
 	* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
@@ -66,7 +63,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 		nodeoffset = fdt_path_offset(blob, "/aliases");
 		if (nodeoffset >= 0) {
-#if defined(CONFIG_HAS_ETH0)
 			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
 			if (prop) {
 				u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
@@ -78,8 +74,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 					fdt_setprop(blob, path, "interrupts",
 						    &tmp, sizeof(tmp));
 			}
-#endif
-#if defined(CONFIG_HAS_ETH1)
 			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
 			if (prop) {
 				u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
@@ -91,11 +85,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 					fdt_setprop(blob, path, "interrupts",
 						    &tmp, sizeof(tmp));
 			}
-#endif
 		}
 	}
 #endif
-#endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"timebase-frequency", (bd->bi_busfreq / 4), 1);
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c308447..c1b4e94 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -317,6 +317,7 @@ config ARCH_MPC8540
 
 config ARCH_MPC8544
 	bool
+	select BTB
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A005125
@@ -330,6 +331,7 @@ config ARCH_MPC8544
 
 config ARCH_MPC8548
 	bool
+	select BTB
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_NMG_DDR120
@@ -352,6 +354,8 @@ config ARCH_MPC8560
 
 config ARCH_P1010
 	bool
+	select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
+	select BTB
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_5
 	select SYS_HAS_SERDES
@@ -400,6 +404,7 @@ config ARCH_P1011
 
 config ARCH_P1020
 	bool
+	select BTB
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A004508
@@ -496,6 +501,7 @@ config ARCH_P1025
 
 config ARCH_P2020
 	bool
+	select BTB
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A004477
@@ -517,6 +523,7 @@ config ARCH_P2020
 
 config ARCH_P2041
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
@@ -542,6 +549,7 @@ config ARCH_P2041
 
 config ARCH_P3041
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
@@ -572,6 +580,7 @@ config ARCH_P3041
 
 config ARCH_P4080
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
@@ -611,6 +620,7 @@ config ARCH_P4080
 
 config ARCH_P5040
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
@@ -641,7 +651,9 @@ config ARCH_QEMU_E500
 
 config ARCH_T1024
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
+	select E5500
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -664,7 +676,9 @@ config ARCH_T1024
 
 config ARCH_T1040
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
+	select E5500
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -687,7 +701,9 @@ config ARCH_T1040
 
 config ARCH_T1042
 	bool
+	select BACKSIDE_L2_CACHE
 	select E500MC
+	select E5500
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -772,6 +788,9 @@ config MPC85XX_HAVE_RESET_VECTOR
 	bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
 	depends on MPC85xx
 
+config BTB
+	bool "toggle branch predition"
+
 config BOOKE
 	bool
 	default y
@@ -784,12 +803,17 @@ config E500
 
 config E500MC
 	bool
+	select BTB
 	imply CMD_PCI
 	help
 		Enble PowerPC E500MC core
 
+config E5500
+	bool
+
 config E6500
 	bool
+	select BTB
 	help
 		Enable PowerPC E6500 core
 
@@ -868,6 +892,18 @@ config SYS_CCSRBAR_DEFAULT
 		if changed by pre-boot regime. The value here must match
 		the current value in SoC. If not sure, do not change.
 
+config A003399_NOR_WORKAROUND
+	bool
+	help
+	  Enables a workaround for IFC erratum A003399. It is only required
+	  during NOR boot.
+
+config A008044_WORKAROUND
+	bool
+	help
+	  Enables a workaround for T1040/T1042 erratum A008044. It is only
+	  required during NAND boot and valid for Rev 1.0 SoC revision
+
 config SYS_FSL_ERRATUM_A004468
 	bool
 
@@ -950,6 +986,7 @@ config SYS_FSL_ERRATUM_A007907
 
 config SYS_FSL_ERRATUM_A008044
 	bool
+	select A008044_WORKAROUND if MTD_RAW_NAND
 
 config SYS_FSL_ERRATUM_CPC_A002
 	bool
@@ -1084,6 +1121,9 @@ config SYS_NUM_TLBCAMS
 		Number of TLB CAM entries for Book-E chips. 64 for E500MC,
 		16 for other E500 SoCs.
 
+config BACKSIDE_L2_CACHE
+	bool
+
 config SYS_PPC64
 	bool
 
@@ -1159,7 +1199,6 @@ source "board/freescale/t104xrdb/Kconfig"
 source "board/freescale/t208xqds/Kconfig"
 source "board/freescale/t208xrdb/Kconfig"
 source "board/freescale/t4rdb/Kconfig"
-source "board/keymile/Kconfig"
 source "board/socrates/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6f4ad1f..c32cde0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MP)	+= release.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
 endif
-obj-$(CONFIG_CPM2)	+= commproc.o
 
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_CORENET) += liodn.o
@@ -49,7 +48,6 @@ obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
 
 
 obj-$(CONFIG_QE)	+= qe_io.o
-obj-$(CONFIG_CPM2)	+= serial_scc.o
 obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c
deleted file mode 100644
index 8e8427a..0000000
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Adapted for Motorola MPC8560 chips
- * Xianghua Xiao <x.xiao@motorola.com>
- *
- * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
- * copyright notice:
- *
- * General Purpose functions for the global management of the
- * 8220 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
- *	2.3.99 Updates
- * Copyright (c) 2003 Motorola,Inc.
- *
- * In addition to the individual control of the communication
- * channels, there are a few functions that globally affect the
- * communication processor.
- *
- * Buffer descriptors must be allocated from the dual ported memory
- * space.  The allocator for that is here.  When the communication
- * process is reset, we reclaim the memory available.  There is
- * currently no deallocator for this memory.
- */
-#include <common.h>
-#include <asm-offsets.h>
-#include <asm/cpm_85xx.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * because we have stack and init data in dual port ram
- * we must reduce the size
- */
-#undef	CPM_DATAONLY_SIZE
-#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-
-void
-m8560_cpm_reset(void)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	volatile ulong count;
-
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Reclaim the DP memory for our use.
-	*/
-	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
-
-	/*
-	 * Reset CPM
-	 */
-	cpm->im_cpm_cp.cpcr = CPM_CR_RST;
-	count = 0;
-	do {			/* Spin until command processed		*/
-		__asm__ __volatile__ ("eieio");
-	} while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
-}
-
-/* Allocate some memory from the dual ported ram.
- * To help protocols with object alignment restrictions, we do that
- * if they ask.
- */
-uint
-m8560_cpm_dpalloc(uint size, uint align)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	uint	retloc;
-	uint	align_mask, off;
-	uint	savebase;
-
-	align_mask = align - 1;
-	savebase = gd->arch.dp_alloc_base;
-
-	off = gd->arch.dp_alloc_base & align_mask;
-	if (off != 0)
-		gd->arch.dp_alloc_base += (align - off);
-
-	if ((off = size & align_mask) != 0)
-		size += align - off;
-
-	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
-		gd->arch.dp_alloc_base = savebase;
-		panic("m8560_cpm_dpalloc: ran out of dual port ram!");
-	}
-
-	retloc = gd->arch.dp_alloc_base;
-	gd->arch.dp_alloc_base += size;
-
-	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
-
-	return(retloc);
-}
-
-/* We also own one page of host buffer space for the allocation of
- * UART "fifos" and the like.
- */
-uint
-m8560_cpm_hostalloc(uint size, uint align)
-{
-	/* the host might not even have RAM yet - just use dual port RAM */
-	return (m8560_cpm_dpalloc(size, align));
-}
-
-/* Set a baud rate generator.  This needs lots of work.  There are
- * eight BRGs, which can be connected to the CPM channels or output
- * as clocks.  The BRGs are in two different block of internal
- * memory mapped space.
- * The baud rate clock is the system clock divided by something.
- * It was set up long ago during the initial boot phase and is
- * is given to us.
- * Baud rate clocks are zero-based in the driver code (as that maps
- * to port numbers).  Documentation uses 1-based numbering.
- */
-#define BRG_INT_CLK	gd->arch.brg_clk
-#define BRG_UART_CLK	((BRG_INT_CLK + 15) / 16)
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-void
-m8560_cpm_setbrg(uint brg, uint rate)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	volatile uint	*bp;
-
-	/* This is good enough to get SMCs running.....
-	*/
-	if (brg < 4) {
-		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-	}
-	else {
-		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-		brg -= 4;
-	}
-	bp += brg;
-	*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-void
-m8560_cpm_fastbrg(uint brg, uint rate, int div16)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	volatile uint	*bp;
-
-	/* This is good enough to get SMCs running.....
-	*/
-	if (brg < 4) {
-		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-	}
-	else {
-		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-		brg -= 4;
-	}
-	bp += brg;
-	*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-	if (div16)
-		*bp |= CPM_BRG_DIV16;
-}
-
-/* This function is used to set baud rate generators using an external
- * clock source and 16x oversampling.
- */
-
-void
-m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	volatile uint	*bp;
-
-	if (brg < 4) {
-		bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
-	}
-	else {
-		bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
-		brg -= 4;
-	}
-	bp += brg;
-	*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
-	if (pinsel == 0)
-		*bp |= CPM_BRG_EXTC_CLK3_9;
-	else
-		*bp |= CPM_BRG_EXTC_CLK5_15;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index cd32290..cc1d02d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -241,10 +241,6 @@ int checkcpu (void)
 	printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
 #endif
 
-#ifdef CONFIG_CPM2
-	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
-#endif
-
 #ifdef CONFIG_QE
 	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01..e9e133b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -152,70 +152,6 @@ static void config_qe_ioports(void)
 }
 #endif
 
-#ifdef CONFIG_CPM2
-void config_8560_ioports (volatile ccsr_cpm_t * cpm)
-{
-	int portnum;
-
-	for (portnum = 0; portnum < 4; portnum++) {
-		uint pmsk = 0,
-		     ppar = 0,
-		     psor = 0,
-		     pdir = 0,
-		     podr = 0,
-		     pdat = 0;
-		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
-		iop_conf_t *eiopc = iopc + 32;
-		uint msk = 1;
-
-		/*
-		 * NOTE:
-		 * index 0 refers to pin 31,
-		 * index 31 refers to pin 0
-		 */
-		while (iopc < eiopc) {
-			if (iopc->conf) {
-				pmsk |= msk;
-				if (iopc->ppar)
-					ppar |= msk;
-				if (iopc->psor)
-					psor |= msk;
-				if (iopc->pdir)
-					pdir |= msk;
-				if (iopc->podr)
-					podr |= msk;
-				if (iopc->pdat)
-					pdat |= msk;
-			}
-
-			msk <<= 1;
-			iopc++;
-		}
-
-		if (pmsk != 0) {
-			volatile ioport_t *iop = ioport_addr (cpm, portnum);
-			uint tpmsk = ~pmsk;
-
-			/*
-			 * the (somewhat confused) paragraph at the
-			 * bottom of page 35-5 warns that there might
-			 * be "unknown behaviour" when programming
-			 * PSORx and PDIRx, if PPARx = 1, so I
-			 * decided this meant I had to disable the
-			 * dedicated function first, and enable it
-			 * last.
-			 */
-			iop->ppar &= tpmsk;
-			iop->psor = (iop->psor & tpmsk) | psor;
-			iop->podr = (iop->podr & tpmsk) | podr;
-			iop->pdat = (iop->pdat & tpmsk) | pdat;
-			iop->pdir = (iop->pdir & tpmsk) | pdir;
-			iop->ppar |= ppar;
-		}
-	}
-}
-#endif
-
 #ifdef CONFIG_SYS_FSL_CPC
 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 void disable_cpc_sram(void)
@@ -474,16 +410,8 @@ ulong cpu_init_f(void)
 #endif
 #endif
 
-#ifdef CONFIG_CPM2
-	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
-#endif
-
        init_early_memctl_regs();
 
-#if defined(CONFIG_CPM2)
-	m8560_cpm_reset();
-#endif
-
 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 	/* Config QE ioports */
 	config_qe_ioports();
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d4b828e..c8ad6a1 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -652,14 +652,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 		"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
-#ifdef CONFIG_CPM2
-	do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
-		"current-speed", gd->baudrate, 1);
-
-	do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
-		"clock-frequency", bd->bi_brgfreq, 1);
-#endif
-
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 		"clock-frequency", get_board_sys_clk(), 1);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index b1b002c..84eb8b4 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -456,18 +456,18 @@ void setup_mp(void)
 	flush_cache(bootpg, 4096);
 
 	/* look for the tlb covering the reset page, there better be one */
-	i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+	i = find_tlb_idx((void *)BPTR_VIRT_ADDR, 1);
 
 	/* we found a match */
 	if (i != -1) {
 		/* map reset page to bootpg so we can copy code there */
 		disable_tlb(i);
 
-		set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
+		set_tlb(1, BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
-		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
+		memcpy((void *)BPTR_VIRT_ADDR, (void *)fixup, 4096);
 
 		plat_mp_up(bootpg_map, pagesize);
 	} else {
diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c
deleted file mode 100644
index a2505d1..0000000
--- a/arch/powerpc/cpu/mpc85xx/serial_scc.c
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- * Modified based on 8260 for 8560.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
- */
-
-/*
- * Minimal serial functions needed to use one of the SCC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <asm/cpm_85xx.h>
-#include <serial.h>
-#include <asm/global_data.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONS_ON_SCC)
-
-#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
-
-#define SCC_INDEX		0
-#define PROFF_SCC		PROFF_SCC1
-#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
-					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */
-
-#define SCC_INDEX		1
-#define PROFF_SCC		PROFF_SCC2
-#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
-					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */
-
-#define SCC_INDEX		2
-#define PROFF_SCC		PROFF_SCC3
-#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
-					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
-
-#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */
-
-#define SCC_INDEX		3
-#define PROFF_SCC		PROFF_SCC4
-#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
-					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
-#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
-#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
-#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
-
-#else
-
-#error "console not correctly defined"
-
-#endif
-
-static int mpc85xx_serial_init(void)
-{
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	volatile ccsr_cpm_scc_t *sp;
-	volatile scc_uart_t *up;
-	volatile cbd_t *tbdf, *rbdf;
-	volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
-	uint	dpaddr;
-
-	/* initialize pointers to SCC */
-
-	sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
-	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-
-	/* Disable transmitter/receiver.
-	*/
-	sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-	/* put the SCC channel into NMSI (non multiplexd serial interface)
-	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
-	 */
-	cpm->im_cpm_mux.cmxscr = \
-		(cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
-
-	/* Set up the baud rate generator.
-	*/
-	serial_setbrg ();
-
-	/* Allocate space for two buffer descriptors in the DP ram.
-	 * damm: allocating space after the two buffers for rx/tx data
-	 */
-
-	dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
-
-	/* Set the physical address of the host memory buffers in
-	 * the buffer descriptors.
-	 */
-	rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
-	rbdf->cbd_bufaddr = (uint) (rbdf+2);
-	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
-	tbdf = rbdf + 1;
-	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
-	tbdf->cbd_sc = BD_SC_WRAP;
-
-	/* Set up the uart parameters in the parameter ram.
-	*/
-	up->scc_genscc.scc_rbase = dpaddr;
-	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
-	up->scc_genscc.scc_rfcr = CPMFCR_EB;
-	up->scc_genscc.scc_tfcr = CPMFCR_EB;
-	up->scc_genscc.scc_mrblr = 1;
-	up->scc_maxidl = 0;
-	up->scc_brkcr = 1;
-	up->scc_parec = 0;
-	up->scc_frmec = 0;
-	up->scc_nosec = 0;
-	up->scc_brkec = 0;
-	up->scc_uaddr1 = 0;
-	up->scc_uaddr2 = 0;
-	up->scc_toseq = 0;
-	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
-	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
-	up->scc_rccm = 0xc0ff;
-
-	/* Mask all interrupts and remove anything pending.
-	*/
-	sp->sccm = 0;
-	sp->scce = 0xffff;
-
-	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
-	*/
-	sp->gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
-	sp->gsmrl = \
-		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
-
-	/* Set CTS no flow control, 1 stop bit, 8 bit character length,
-	 * normal async UART mode, no parity
-	 */
-	sp->psmr = SCU_PSMR_CL;
-
-	/* execute the "Init Rx and Tx params" CP command.
-	*/
-
-	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
-					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
-	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
-	  ;
-
-	/* Enable transmitter/receiver.
-	*/
-	sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
-
-	return (0);
-}
-
-static void mpc85xx_serial_setbrg(void)
-{
-#if defined(CONFIG_CONS_USE_EXTC)
-	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
-		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
-#else
-	m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
-#endif
-}
-
-static void mpc85xx_serial_putc(const char c)
-{
-	volatile scc_uart_t	*up;
-	volatile cbd_t		*tbdf;
-	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-	tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
-
-	/* Wait for last character to go.
-	 */
-	while (tbdf->cbd_sc & BD_SC_READY)
-		;
-
-	/* Load the character into the transmit buffer.
-	 */
-	*(volatile char *)tbdf->cbd_bufaddr = c;
-	tbdf->cbd_datlen = 1;
-	tbdf->cbd_sc |= BD_SC_READY;
-}
-
-static int mpc85xx_serial_getc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	unsigned char		c;
-
-	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
-
-	/* Wait for character to show up.
-	 */
-	while (rbdf->cbd_sc & BD_SC_EMPTY)
-		;
-
-	/* Grab the char and clear the buffer again.
-	 */
-	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
-	rbdf->cbd_sc |= BD_SC_EMPTY;
-
-	return (c);
-}
-
-static int mpc85xx_serial_tstc(void)
-{
-	volatile cbd_t		*rbdf;
-	volatile scc_uart_t	*up;
-	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
-	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
-	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
-
-	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
-}
-
-static struct serial_device mpc85xx_serial_drv = {
-	.name	= "mpc85xx_serial",
-	.start	= mpc85xx_serial_init,
-	.stop	= NULL,
-	.setbrg	= mpc85xx_serial_setbrg,
-	.putc	= mpc85xx_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= mpc85xx_serial_getc,
-	.tstc	= mpc85xx_serial_tstc,
-};
-
-void mpc85xx_serial_initialize(void)
-{
-	serial_register(&mpc85xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &mpc85xx_serial_drv;
-}
-#endif	/* CONFIG_CONS_ON_SCC */
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 5a9cd28..4b6f3d2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -581,15 +581,6 @@ int get_clocks(void)
 #ifdef CONFIG_ARCH_MPC8544
 	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
-#if defined(CONFIG_CPM2)
-	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-	uint sccr, dfbrg;
-
-	/* set VCO = 4 * BRG */
-	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
-	sccr = cpm->im_cpm_intctl.sccr;
-	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
-#endif
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus;
@@ -635,13 +626,6 @@ int get_clocks(void)
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
-#if defined(CONFIG_CPM2)
-	gd->arch.vco_out = 2*sys_info.freq_systembus;
-	gd->arch.cpm_clk = gd->arch.vco_out / 2;
-	gd->arch.scc_clk = gd->arch.vco_out / 4;
-	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
-#endif
-
 	if(gd->cpu_clk != 0) return (0);
 	else return (1);
 }
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 656cc6e..9ddd371 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -247,7 +247,7 @@ l2_disabled:
 /* Interrupt vectors do not fit in minimal SPL. */
 #if !defined(MINIMAL_SPL)
 	/* Setup interrupt vectors */
-	lis	r1,CONFIG_SYS_MONITOR_BASE@h
+	lis	r1,CONFIG_VAL(SYS_MONITOR_BASE)@h
 	mtspr	IVPR,r1
 
 	li	r4,CriticalInput@l
@@ -450,7 +450,7 @@ nexti:	mflr	r1		/* R1 = our PC */
  */
 	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
 		0, BOOKE_PAGESZ_4M, \
-		CONFIG_SYS_MONITOR_BASE & 0xffc00000,  MAS2_I|MAS2_G, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xffc00000,  MAS2_I|MAS2_G, \
 		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
@@ -461,8 +461,8 @@ nexti:	mflr	r1		/* R1 = our PC */
  */
 	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
 		0, BOOKE_PAGESZ_256K, \
-		CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
-		CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfffc0000, MAS2_I, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #endif
 #endif
@@ -1027,7 +1027,7 @@ create_init_ram_area:
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_4M, \
-		CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xffc00000, MAS2_I|MAS2_G, \
 		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
@@ -1037,7 +1037,7 @@ create_init_ram_area:
 	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
@@ -1048,24 +1048,24 @@ create_init_ram_area:
  */
 #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
 	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
-	/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+	/* create a temp mapping in AS = 1 for mapping CONFIG_VAL(SYS_MONITOR_BASE)
 	 * to L3 Address configured by PBL for ISBC code
 	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
 #else
 	/*
-	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
-	 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
+	 * create a temp mapping in AS=1 to the 1M CONFIG_VAL(SYS_MONITOR_BASE) space, the main
+	 * image has been relocated to CONFIG_VAL(SYS_MONITOR_BASE) on the second stage.
 	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #endif
 
@@ -1126,8 +1126,8 @@ switch_as:
 #else
 	/* Calculate absolute address in FLASH and jump there		*/
 	/*--------------------------------------------------------------*/
-	lis	r3,CONFIG_SYS_MONITOR_BASE@h
-	ori	r3,r3,CONFIG_SYS_MONITOR_BASE@l
+	lis	r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
+	ori	r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
 	addi	r3,r3,_start_cont - _start
 	mtlr	r3
 	blr
@@ -1530,8 +1530,8 @@ relocate_code:
 	GET_GOT
 #ifndef CONFIG_SPL_SKIP_RELOCATE
 	mr	r3,r5				/* Destination Address	*/
-	lis	r4,CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
-	ori	r4,r4,CONFIG_SYS_MONITOR_BASE@l
+	lis	r4,CONFIG_VAL(SYS_MONITOR_BASE)@h		/* Source      Address	*/
+	ori	r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l
 	lwz	r5,GOT(__init_end)
 	sub	r5,r5,r4
 	li	r6,CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
@@ -1539,7 +1539,7 @@ relocate_code:
 	/*
 	 * Fix GOT pointer:
 	 *
-	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_VAL(SYS_MONITOR_BASE)) + Destination Address
 	 *
 	 * Offset:
 	 */
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 3541371..059ffe1 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -31,9 +31,7 @@
  * Freescale's default e500 reset page.
  */
 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
-#ifndef CONFIG_BPTR_VIRT_ADDR
-#define CONFIG_BPTR_VIRT_ADDR	0xfffff000
-#endif
+#define BPTR_VIRT_ADDR	0xfffff000
 #endif
 
 /* Since so many PPC SOCs have a semi-common LBC, define this here */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7eb4566..47bfcc7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -270,7 +270,6 @@
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_E5500
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
@@ -299,7 +298,6 @@
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_E5500
 #define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
deleted file mode 100644
index d42469c..0000000
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ /dev/null
@@ -1,824 +0,0 @@
-/*
- * MPC85xx Communication Processor Module
- * Copyright (c) 2003,Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- *
- * MPC8260 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the MPC8260 internal
- * memory map.  See immap.h for details.
- */
-#ifndef __CPM_85XX__
-#define __CPM_85XX__
-
-#include <asm/immap_85xx.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((uint)0x80000000)
-#define CPM_CR_PAGE	((uint)0x7c000000)
-#define CPM_CR_SBLOCK	((uint)0x03e00000)
-#define CPM_CR_FLG	((uint)0x00010000)
-#define CPM_CR_MCN	((uint)0x00003fc0)
-#define CPM_CR_OPCODE	((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK	(0x04)
-#define CPM_CR_SCC2_SBLOCK	(0x05)
-#define CPM_CR_SCC3_SBLOCK	(0x06)
-#define CPM_CR_SCC4_SBLOCK	(0x07)
-#define CPM_CR_SMC1_SBLOCK	(0x08)
-#define CPM_CR_SMC2_SBLOCK	(0x09)
-#define CPM_CR_SPI_SBLOCK	(0x0a)
-#define CPM_CR_I2C_SBLOCK	(0x0b)
-#define CPM_CR_TIMER_SBLOCK	(0x0f)
-#define CPM_CR_RAND_SBLOCK	(0x0e)
-#define CPM_CR_FCC1_SBLOCK	(0x10)
-#define CPM_CR_FCC2_SBLOCK	(0x11)
-#define CPM_CR_FCC3_SBLOCK	(0x12)
-#define CPM_CR_MCC1_SBLOCK	(0x1c)
-
-#define CPM_CR_SCC1_PAGE	(0x00)
-#define CPM_CR_SCC2_PAGE	(0x01)
-#define CPM_CR_SCC3_PAGE	(0x02)
-#define CPM_CR_SCC4_PAGE	(0x03)
-#define CPM_CR_SPI_PAGE		(0x09)
-#define CPM_CR_I2C_PAGE		(0x0a)
-#define CPM_CR_TIMER_PAGE	(0x0a)
-#define CPM_CR_RAND_PAGE	(0x0a)
-#define CPM_CR_FCC1_PAGE	(0x04)
-#define CPM_CR_FCC2_PAGE	(0x05)
-#define CPM_CR_FCC3_PAGE	(0x06)
-#define CPM_CR_MCC1_PAGE	(0x07)
-#define CPM_CR_MCC2_PAGE	(0x08)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE	((uint)128)
-#define CPM_DP_NOSPACE		((uint)0x7FFFFFFF)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x0000B000)
-#define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES	2
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-/*extern	cpm8560_t	*cpmp;	 Pointer to comm processor */
-uint		m8560_cpm_dpalloc(uint size, uint align);
-uint		m8560_cpm_hostalloc(uint size, uint align);
-void		m8560_cpm_setbrg(uint brg, uint rate);
-void		m8560_cpm_fastbrg(uint brg, uint rate, int div16);
-void		m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_CD	((ushort)0x0001)	/* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
-#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
-#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
-#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
-#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
-#define PROFF_SCC1		((uint)0x8000)
-#define PROFF_SCC2		((uint)0x8100)
-#define PROFF_SCC3		((uint)0x8200)
-#define PROFF_SCC4		((uint)0x8300)
-#define PROFF_FCC1		((uint)0x8400)
-#define PROFF_FCC2		((uint)0x8500)
-#define PROFF_FCC3		((uint)0x8600)
-#define PROFF_MCC1		((uint)0x8700)
-#define PROFF_MCC2		((uint)0x8800)
-#define PROFF_SPI_BASE		((uint)0x89fc)
-#define PROFF_TIMERS		((uint)0x8ae0)
-#define PROFF_REVNUM		((uint)0x8af0)
-#define PROFF_RAND		((uint)0x8af8)
-#define PROFF_I2C_BASE		((uint)0x8afc)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define	SCCM_TXE	((unsigned char)0x10)
-#define	SCCM_BSY	((unsigned char)0x04)
-#define	SCCM_TX		((unsigned char)0x02)
-#define	SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY	((ushort)0x8000)
-#define BD_ENET_RX_WRAP		((ushort)0x2000)
-#define BD_ENET_RX_INTR		((ushort)0x1000)
-#define BD_ENET_RX_LAST		((ushort)0x0800)
-#define BD_ENET_RX_FIRST	((ushort)0x0400)
-#define BD_ENET_RX_MISS		((ushort)0x0100)
-#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
-#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
-#define BD_ENET_RX_LG		((ushort)0x0020)
-#define BD_ENET_RX_NO		((ushort)0x0010)
-#define BD_ENET_RX_SH		((ushort)0x0008)
-#define BD_ENET_RX_CR		((ushort)0x0004)
-#define BD_ENET_RX_OV		((ushort)0x0002)
-#define BD_ENET_RX_CL		((ushort)0x0001)
-#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY	((ushort)0x8000)
-#define BD_ENET_TX_PAD		((ushort)0x4000)
-#define BD_ENET_TX_WRAP		((ushort)0x2000)
-#define BD_ENET_TX_INTR		((ushort)0x1000)
-#define BD_ENET_TX_LAST		((ushort)0x0800)
-#define BD_ENET_TX_TC		((ushort)0x0400)
-#define BD_ENET_TX_DEF		((ushort)0x0200)
-#define BD_ENET_TX_HB		((ushort)0x0100)
-#define BD_ENET_TX_LC		((ushort)0x0080)
-#define BD_ENET_TX_RL		((ushort)0x0040)
-#define BD_ENET_TX_RCMASK	((ushort)0x003c)
-#define BD_ENET_TX_UN		((ushort)0x0002)
-#define BD_ENET_TX_CSL		((ushort)0x0001)
-#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	uint	scc_res1;	/* Reserved */
-	uint	scc_res2;	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST		((ushort)0x0800)
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
-#define FCC_GFMR_TCI		((uint)0x20000000)
-#define FCC_GFMR_TRX		((uint)0x10000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_CDP		((uint)0x04000000)
-#define FCC_GFMR_CTSP		((uint)0x02000000)
-#define FCC_GFMR_CDS		((uint)0x01000000)
-#define FCC_GFMR_CTSS		((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
-#define FCC_GFMR_SYNL_8		((uint)0x00008000)
-#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
-#define FCC_GFMR_RTSM		((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
-#define FCC_GFMR_REVD		((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
-#define FCC_GFMR_TCRC_16	((uint)0x00000000)
-#define FCC_GFMR_TCRC_32	((uint)0x00000080)
-#define FCC_GFMR_ENR		((uint)0x00000020)
-#define FCC_GFMR_ENT		((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-	ushort	fcc_riptr;	/* Rx Internal temp pointer */
-	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
-	ushort	fcc_res1;
-	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
-	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_rbase;	/* Receive BD base */
-	ushort	fcc_rbdstat;	/* RxBD status */
-	ushort	fcc_rbdlen;	/* RxBD down counter */
-	uint	fcc_rdptr;	/* RxBD internal data pointer */
-	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_tbase;	/* Transmit BD base */
-	ushort	fcc_tbdstat;	/* TxBD status */
-	ushort	fcc_tbdlen;	/* TxBD down counter */
-	uint	fcc_tdptr;	/* TxBD internal data pointer */
-	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
-	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
-	uint	fcc_rcrc;	/* Rx temp CRC */
-	uint	fcc_res2;
-	uint	fcc_tcrc;	/* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-	fccp_t	fen_genfcc;
-	uint	fen_statbuf;	/* Internal status buffer */
-	uint	fen_camptr;	/* CAM address */
-	uint	fen_cmask;	/* Constant mask for CRC */
-	uint	fen_cpres;	/* Preset CRC */
-	uint	fen_crcec;	/* CRC Error counter */
-	uint	fen_alec;	/* alignment error counter */
-	uint	fen_disfc;	/* discard frame counter */
-	ushort	fen_retlim;	/* Retry limit */
-	ushort	fen_retcnt;	/* Retry counter */
-	ushort	fen_pper;	/* Persistence */
-	ushort	fen_boffcnt;	/* backoff counter */
-	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
-	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
-	ushort	fen_tfcstat;	/* out of sequence TxBD */
-	ushort	fen_tfclen;
-	uint	fen_tfcptr;
-	ushort	fen_mflr;	/* Maximum frame length (1518) */
-	ushort	fen_paddrh;	/* MAC address */
-	ushort	fen_paddrm;
-	ushort	fen_paddrl;
-	ushort	fen_ibdcount;	/* Internal BD counter */
-	ushort	fen_ibdstart;	/* Internal BD start pointer */
-	ushort	fen_ibdend;	/* Internal BD end pointer */
-	ushort	fen_txlen;	/* Internal Tx frame length counter */
-	uint	fen_ibdbase[8]; /* Internal use */
-	uint	fen_iaddrh;	/* Individual address filter */
-	uint	fen_iaddrl;
-	ushort	fen_minflr;	/* Minimum frame length (64) */
-	ushort	fen_taddrh;	/* Filter transfer MAC address */
-	ushort	fen_taddrm;
-	ushort	fen_taddrl;
-	ushort	fen_padptr;	/* Pointer to pad byte buffer */
-	ushort	fen_cftype;	/* control frame type */
-	ushort	fen_cfrange;	/* control frame range */
-	ushort	fen_maxb;	/* maximum BD count */
-	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
-	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
-	ushort	fen_maxd;	/* internal max DMA count */
-	ushort	fen_dmacnt;	/* internal DMA counter */
-	uint	fen_octc;	/* Total octect counter */
-	uint	fen_colc;	/* Total collision counter */
-	uint	fen_broc;	/* Total broadcast packet counter */
-	uint	fen_mulc;	/* Total multicast packet count */
-	uint	fen_uspc;	/* Total packets < 64 bytes */
-	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
-	uint	fen_ospc;	/* Total packets > 1518 */
-	uint	fen_jbrc;	/* Total packets > 1518 with errors */
-	uint	fen_p64c;	/* Total packets == 64 bytes */
-	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
-	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
-	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
-	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
-	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
-	uint	fen_cambuf;	/* Internal CAM buffer poiner */
-	ushort	fen_rfthr;	/* Received frames threshold */
-	ushort	fen_rfcnt;	/* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
-#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
-#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
-#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
-#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
-#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
-#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
-#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
-#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
-#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
-#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
-#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
-#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
-	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
-	u_char	spi_rfcr;	/* Rx function code */
-	u_char	spi_tfcr;	/* Tx function code */
-	ushort	spi_mrblr;	/* Max receive buffer length */
-	uint	spi_rstate;	/* Internal */
-	uint	spi_rdp;	/* Internal */
-	ushort	spi_rbptr;	/* Internal */
-	ushort	spi_rbc;	/* Internal */
-	uint	spi_rxtmp;	/* Internal */
-	uint	spi_tstate;	/* Internal */
-	uint	spi_tdp;	/* Internal */
-	ushort	spi_tbptr;	/* Internal */
-	ushort	spi_tbc;	/* Internal */
-	uint	spi_txtmp;	/* Internal */
-	uint	spi_res;	/* Tx temp. */
-	uint	spi_res1[4];	/* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
-#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
-#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
-#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
-#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
-#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
-#define SPMODE_EN	((ushort)0x0100)	/* Enable */
-#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
-#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
-
-#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)	((x) &0xF)
-
-#define SPI_EB		((u_char)0x10)		/* big endian byte order */
-
-#define BD_IIC_START	((ushort)0x0400)
-
-/*-----------------------------------------------------------------------
- * CMXFCR - CMX FCC Clock Route Register                                15-12
- */
-#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
-#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
-#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
-#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
-#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
-#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
-#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
-#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
-#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
-
-#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
-#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
-#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
-#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
-#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
-#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
-#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
-#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
-#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
-#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
-#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
-#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
-#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
-#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
-#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
-#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
-#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
-#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
-#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
-#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
-#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
-#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
-#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
-#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
-#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
-#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
-#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
-#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
-#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
-#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
-#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
-#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
-#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
-#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
-#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
-#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
-
-#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
-#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
-#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
-#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
-#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
-#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
-#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
-#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
-
-/*-----------------------------------------------------------------------
- * CMXSCR - CMX SCC Clock Route Register                                15-14
- */
-#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
-#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
-#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
-#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
-#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
-#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
-#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
-#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
-#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
-#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
-#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
-#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
-#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
-#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
-#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
-#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
-
-#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
-#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
-#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
-#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
-#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
-#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
-#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
-#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
-#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
-#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
-#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
-#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
-#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
-#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
-#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
-#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
-#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
-#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
-#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
-#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
-#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
-#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
-#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
-#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
-#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
-#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
-#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
-#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
-#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
-#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
-#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
-#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
-#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
-#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
-#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
-#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
-#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
-#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
-#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
-#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
-#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
-#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
-#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
-
-#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
-#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
-#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
-#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
-#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
-#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
-#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
-#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
-#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
-#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
-#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
-#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
-#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
-#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
-#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
-
-#endif /* __CPM_85XX__ */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2975255..770adcd 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -20,13 +20,6 @@ struct arch_global_data {
 #if defined(CONFIG_MPC8xx)
 	unsigned long brg_clk;
 #endif
-#if defined(CONFIG_CPM2)
-	/* There are many clocks on the MPC8260 - see page 9-5 */
-	unsigned long vco_out;
-	unsigned long cpm_clk;
-	unsigned long scc_clk;
-	unsigned long brg_clk;
-#endif
 	/* TODO: sjg@chromium.org: Should these be unslgned long? */
 #if defined(CONFIG_MPC83xx)
 #ifdef CONFIG_CLK_MPC83XX
@@ -88,10 +81,6 @@ struct arch_global_data {
 	unsigned long arbiter_event_attributes;
 	unsigned long arbiter_event_address;
 #endif
-#if defined(CONFIG_CPM2)
-	unsigned int dp_alloc_base;
-	unsigned int dp_alloc_top;
-#endif
 #ifdef CONFIG_SYS_FPGA_COUNT
 	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 #endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 770705a..b8bc584 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -921,330 +921,6 @@ typedef struct ccsr_pic {
 	u8	res150[130892];
 } ccsr_pic_t;
 
-/* CPM Block */
-#ifndef CONFIG_CPM2
-typedef struct ccsr_cpm {
-	u8 res[262144];
-} ccsr_cpm_t;
-#else
-/*
- * DPARM
- * General SIU
- */
-typedef struct ccsr_cpm_siu {
-	u8	res1[80];
-	u32	smaer;
-	u32	smser;
-	u32	smevr;
-	u8	res2[4];
-	u32	lmaer;
-	u32	lmser;
-	u32	lmevr;
-	u8	res3[2964];
-} ccsr_cpm_siu_t;
-
-/* IRQ Controller */
-typedef struct ccsr_cpm_intctl {
-	u16	sicr;
-	u8	res1[2];
-	u32	sivec;
-	u32	sipnrh;
-	u32	sipnrl;
-	u32	siprr;
-	u32	scprrh;
-	u32	scprrl;
-	u32	simrh;
-	u32	simrl;
-	u32	siexr;
-	u8	res2[88];
-	u32	sccr;
-	u8	res3[124];
-} ccsr_cpm_intctl_t;
-
-/* input/output port */
-typedef struct ccsr_cpm_iop {
-	u32	pdira;
-	u32	ppara;
-	u32	psora;
-	u32	podra;
-	u32	pdata;
-	u8	res1[12];
-	u32	pdirb;
-	u32	pparb;
-	u32	psorb;
-	u32	podrb;
-	u32	pdatb;
-	u8	res2[12];
-	u32	pdirc;
-	u32	pparc;
-	u32	psorc;
-	u32	podrc;
-	u32	pdatc;
-	u8	res3[12];
-	u32	pdird;
-	u32	ppard;
-	u32	psord;
-	u32	podrd;
-	u32	pdatd;
-	u8	res4[12];
-} ccsr_cpm_iop_t;
-
-/* CPM timers */
-typedef struct ccsr_cpm_timer {
-	u8	tgcr1;
-	u8	res1[3];
-	u8	tgcr2;
-	u8	res2[11];
-	u16	tmr1;
-	u16	tmr2;
-	u16	trr1;
-	u16	trr2;
-	u16	tcr1;
-	u16	tcr2;
-	u16	tcn1;
-	u16	tcn2;
-	u16	tmr3;
-	u16	tmr4;
-	u16	trr3;
-	u16	trr4;
-	u16	tcr3;
-	u16	tcr4;
-	u16	tcn3;
-	u16	tcn4;
-	u16	ter1;
-	u16	ter2;
-	u16	ter3;
-	u16	ter4;
-	u8	res3[608];
-} ccsr_cpm_timer_t;
-
-/* SDMA */
-typedef struct ccsr_cpm_sdma {
-	u8	sdsr;
-	u8	res1[3];
-	u8	sdmr;
-	u8	res2[739];
-} ccsr_cpm_sdma_t;
-
-/* FCC1 */
-typedef struct ccsr_cpm_fcc1 {
-	u32	gfmr;
-	u32	fpsmr;
-	u16	ftodr;
-	u8	res1[2];
-	u16	fdsr;
-	u8	res2[2];
-	u16	fcce;
-	u8	res3[2];
-	u16	fccm;
-	u8	res4[2];
-	u8	fccs;
-	u8	res5[3];
-	u8	ftirr_phy[4];
-} ccsr_cpm_fcc1_t;
-
-/* FCC2 */
-typedef struct ccsr_cpm_fcc2 {
-	u32	gfmr;
-	u32	fpsmr;
-	u16	ftodr;
-	u8	res1[2];
-	u16	fdsr;
-	u8	res2[2];
-	u16	fcce;
-	u8	res3[2];
-	u16	fccm;
-	u8	res4[2];
-	u8	fccs;
-	u8	res5[3];
-	u8	ftirr_phy[4];
-} ccsr_cpm_fcc2_t;
-
-/* FCC3 */
-typedef struct ccsr_cpm_fcc3 {
-	u32	gfmr;
-	u32	fpsmr;
-	u16	ftodr;
-	u8	res1[2];
-	u16	fdsr;
-	u8	res2[2];
-	u16	fcce;
-	u8	res3[2];
-	u16	fccm;
-	u8	res4[2];
-	u8	fccs;
-	u8	res5[3];
-	u8	res[36];
-} ccsr_cpm_fcc3_t;
-
-/* FCC1 extended */
-typedef struct ccsr_cpm_fcc1_ext {
-	u32	firper;
-	u32	firer;
-	u32	firsr_h;
-	u32	firsr_l;
-	u8	gfemr;
-	u8	res[15];
-
-} ccsr_cpm_fcc1_ext_t;
-
-/* FCC2 extended */
-typedef struct ccsr_cpm_fcc2_ext {
-	u32	firper;
-	u32	firer;
-	u32	firsr_h;
-	u32	firsr_l;
-	u8	gfemr;
-	u8	res[31];
-} ccsr_cpm_fcc2_ext_t;
-
-/* FCC3 extended */
-typedef struct ccsr_cpm_fcc3_ext {
-	u8	gfemr;
-	u8	res[47];
-} ccsr_cpm_fcc3_ext_t;
-
-/* TC layers */
-typedef struct ccsr_cpm_tmp1 {
-	u8	res[496];
-} ccsr_cpm_tmp1_t;
-
-/* BRGs:5,6,7,8 */
-typedef struct ccsr_cpm_brg2 {
-	u32	brgc5;
-	u32	brgc6;
-	u32	brgc7;
-	u32	brgc8;
-	u8	res[608];
-} ccsr_cpm_brg2_t;
-
-/* I2C */
-typedef struct ccsr_cpm_i2c {
-	u8	i2mod;
-	u8	res1[3];
-	u8	i2add;
-	u8	res2[3];
-	u8	i2brg;
-	u8	res3[3];
-	u8	i2com;
-	u8	res4[3];
-	u8	i2cer;
-	u8	res5[3];
-	u8	i2cmr;
-	u8	res6[331];
-} ccsr_cpm_i2c_t;
-
-/* CPM core */
-typedef struct ccsr_cpm_cp {
-	u32	cpcr;
-	u32	rccr;
-	u8	res1[14];
-	u16	rter;
-	u8	res2[2];
-	u16	rtmr;
-	u16	rtscr;
-	u8	res3[2];
-	u32	rtsr;
-	u8	res4[12];
-} ccsr_cpm_cp_t;
-
-/* BRGs:1,2,3,4 */
-typedef struct ccsr_cpm_brg1 {
-	u32	brgc1;
-	u32	brgc2;
-	u32	brgc3;
-	u32	brgc4;
-} ccsr_cpm_brg1_t;
-
-/* SCC1-SCC4 */
-typedef struct ccsr_cpm_scc {
-	u32	gsmrl;
-	u32	gsmrh;
-	u16	psmr;
-	u8	res1[2];
-	u16	todr;
-	u16	dsr;
-	u16	scce;
-	u8	res2[2];
-	u16	sccm;
-	u8	res3;
-	u8	sccs;
-	u8	res4[8];
-} ccsr_cpm_scc_t;
-
-typedef struct ccsr_cpm_tmp2 {
-	u8	res[32];
-} ccsr_cpm_tmp2_t;
-
-/* SPI */
-typedef struct ccsr_cpm_spi {
-	u16	spmode;
-	u8	res1[4];
-	u8	spie;
-	u8	res2[3];
-	u8	spim;
-	u8	res3[2];
-	u8	spcom;
-	u8	res4[82];
-} ccsr_cpm_spi_t;
-
-/* CPM MUX */
-typedef struct ccsr_cpm_mux {
-	u8	cmxsi1cr;
-	u8	res1;
-	u8	cmxsi2cr;
-	u8	res2;
-	u32	cmxfcr;
-	u32	cmxscr;
-	u8	res3[2];
-	u16	cmxuar;
-	u8	res4[16];
-} ccsr_cpm_mux_t;
-
-/* SI,MCC,etc */
-typedef struct ccsr_cpm_tmp3 {
-	u8 res[58592];
-} ccsr_cpm_tmp3_t;
-
-typedef struct ccsr_cpm_iram {
-	u32	iram[8192];
-	u8	res[98304];
-} ccsr_cpm_iram_t;
-
-typedef struct ccsr_cpm {
-	/* Some references are into the unique & known dpram spaces,
-	 * others are from the generic base.
-	 */
-#define im_dprambase		im_dpram1
-	u8			im_dpram1[16*1024];
-	u8			res1[16*1024];
-	u8			im_dpram2[16*1024];
-	u8			res2[16*1024];
-	ccsr_cpm_siu_t		im_cpm_siu; /* SIU Configuration */
-	ccsr_cpm_intctl_t	im_cpm_intctl; /* IRQ Controller */
-	ccsr_cpm_iop_t		im_cpm_iop; /* IO Port control/status */
-	ccsr_cpm_timer_t	im_cpm_timer; /* CPM timers */
-	ccsr_cpm_sdma_t		im_cpm_sdma; /* SDMA control/status */
-	ccsr_cpm_fcc1_t		im_cpm_fcc1;
-	ccsr_cpm_fcc2_t		im_cpm_fcc2;
-	ccsr_cpm_fcc3_t		im_cpm_fcc3;
-	ccsr_cpm_fcc1_ext_t	im_cpm_fcc1_ext;
-	ccsr_cpm_fcc2_ext_t	im_cpm_fcc2_ext;
-	ccsr_cpm_fcc3_ext_t	im_cpm_fcc3_ext;
-	ccsr_cpm_tmp1_t		im_cpm_tmp1;
-	ccsr_cpm_brg2_t		im_cpm_brg2;
-	ccsr_cpm_i2c_t		im_cpm_i2c;
-	ccsr_cpm_cp_t		im_cpm_cp;
-	ccsr_cpm_brg1_t		im_cpm_brg1;
-	ccsr_cpm_scc_t		im_cpm_scc[4];
-	ccsr_cpm_tmp2_t		im_cpm_tmp2;
-	ccsr_cpm_spi_t		im_cpm_spi;
-	ccsr_cpm_mux_t		im_cpm_mux;
-	ccsr_cpm_tmp3_t		im_cpm_tmp3;
-	ccsr_cpm_iram_t		im_cpm_iram;
-} ccsr_cpm_t;
-#endif
-
 #ifdef CONFIG_SYS_SRIO
 /* Architectural regsiters */
 struct rio_arch {
@@ -2888,7 +2564,6 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
-#define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
@@ -2965,8 +2640,6 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_CPM_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index d2e5e60..55dcad5 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -27,13 +27,6 @@ int arch_setup_bdinfo(void)
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
 
-#if defined(CONFIG_CPM2)
-	bd->bi_cpmfreq = gd->arch.cpm_clk;
-	bd->bi_brgfreq = gd->arch.brg_clk;
-	bd->bi_sccfreq = gd->arch.scc_clk;
-	bd->bi_vco = gd->arch.vco_out;
-#endif /* CONFIG_CPM2 */
-
 	return 0;
 }
 
@@ -59,10 +52,4 @@ void arch_print_bdinfo(void)
 		puts("addressing  = 32-bit\n");
 #endif
 	board_detail();
-#if defined(CONFIG_CPM2)
-	bdinfo_print_mhz("cpmfreq", bd->bi_cpmfreq);
-	bdinfo_print_mhz("vco", bd->bi_vco);
-	bdinfo_print_mhz("sccfreq", bd->bi_sccfreq);
-	bdinfo_print_mhz("brgfreq", bd->bi_brgfreq);
-#endif
 }
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 8d65047..3b43066 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -266,12 +266,6 @@ static void set_clocks_in_mhz (struct bd_info *kbd)
 		/* convert all clock information to MHz */
 		kbd->bi_intfreq /= 1000000L;
 		kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_CPM2)
-		kbd->bi_cpmfreq /= 1000000L;
-		kbd->bi_brgfreq /= 1000000L;
-		kbd->bi_sccfreq /= 1000000L;
-		kbd->bi_vco	/= 1000000L;
-#endif
 	}
 }