global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace

Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>

29 files changed, 197 insertions, 197 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
index b972cf3..7921334 100644
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -76,7 +76,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index 34b58bb..e53dd43 100644
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 14d5c56..432d4b1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -59,7 +59,7 @@ int checkcpu (void)
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
 	defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
 	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+		(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
 	/*
@@ -124,7 +124,7 @@ int checkcpu (void)
 		puts("Unicore software on multiprocessor system!!\n"
 		     "To enable mutlticore build define CONFIG_MP\n");
 #endif
-		volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+		volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 		printf("CPU%d:  ", pic->whoami);
 	} else {
 		puts("CPU:   ");
@@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	val |= 0x70000000;
 	mtspr(DBCR0,val);
 #else
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* Call board-specific preparation for reset */
 	board_reset_prepare();
@@ -436,7 +436,7 @@ int dram_init(void)
 
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	{
-		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+		ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 		unsigned int x = 10;
 		unsigned int i;
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 90f024d..9fb7802 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -302,7 +302,7 @@ static void corenet_tb_init(void)
 	volatile ccsr_rcpm_t *rcpm =
 		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	volatile ccsr_pic_t *pic =
-		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+		(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 	u32 whoami = in_be32(&pic->whoami);
 
 	/* Enable the timebase register for this core */
@@ -313,7 +313,7 @@ static void corenet_tb_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 void fsl_erratum_a007212_workaround(void)
 {
-	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 ddr_pll_ratio;
 	u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
 	u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
@@ -379,13 +379,13 @@ ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	struct law_entry law;
 #endif
 #ifdef CONFIG_ARCH_MPC8548
-	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
 	uint svr = get_svr();
 
 	/*
@@ -455,7 +455,7 @@ int enable_cluster_l2(void)
 {
 	int i = 0;
 	u32 cluster, svr = get_svr();
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	struct ccsr_cluster_l2 __iomem *l2cache;
 
 	/* only the L2 of first cluster should be enabled as expected on T4080,
@@ -516,7 +516,7 @@ int l2cache_init(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_L2_CACHE
-	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
@@ -821,7 +821,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
-			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+			(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy1);
@@ -833,7 +833,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
-			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+			(void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy2);
@@ -859,7 +859,7 @@ int cpu_init_r(void)
 
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 		struct ccsr_usb_phy __iomem *usb_phy =
-			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+			(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
@@ -928,11 +928,11 @@ int cpu_init_r(void)
 		fsl_sata_reg_t *reg;
 
 		/* first SATA controller */
-		reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+		reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 
 		/* second SATA controller */
-		reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+		reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 	}
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index e6d3058..18bfa2a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #ifdef CONFIG_A003399_NOR_WORKAROUND
-	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
 	int i;
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 61d8aa7..811e6d6 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -222,7 +222,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
 {
-	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 	volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 	u32 ver = SVR_SOC_VER(get_svr());
 
@@ -509,7 +509,7 @@ static void ft_fixup_qe_snum(void *blob)
 #if defined(CONFIG_ARCH_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 	int off;
 
@@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
 {
 	/* the 3rd DMA is not functional if SRIO2 is chosen */
 	int nodeoff;
-	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index da8e0b6..1a30395 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 cfg = in_be32(&gur->rcwsr[4]);
 	int i;
 
@@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2b4912b..1d35733 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane)
 
 int serdes_lane_enabled(int lane)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 
 	int bank = lanes[lane].bank;
@@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* Is serdes enabled at all? */
 	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device)
 	u32 prtcl;
 	const ccsr_gur_t *gur;
 
-	gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
 
 	/* Is serdes enabled at all? */
 	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device)
 	if (unlikely(device == NONE))
 		return;
 
-	gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
 
 	/* Is serdes enabled at all? */
 	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	int cfg;
 	serdes_corenet_t *srds_regs;
 #ifdef CONFIG_ARCH_P5040
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index 4ad7626..bcbdfac 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -25,7 +25,7 @@
 
 void interrupt_init_cpu(unsigned *decrementer_count)
 {
-	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+	ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
 
 #ifdef CONFIG_POST
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 84eb8b4..e1469eb 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -50,7 +50,7 @@ int hold_cores_in_reset(int verbose)
 
 int cpu_reset(u32 nr)
 {
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 	out_be32(&pic->pir, 1 << nr);
 	/* the dummy read works around an errata on early 85xx MP PICs */
 	(void)in_be32(&pic->pir);
@@ -87,7 +87,7 @@ int cpu_status(u32 nr)
 #ifdef CONFIG_FSL_CORENET
 int cpu_disable(u32 nr)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 	setbits_be32(&gur->coredisrl, 1 << nr);
 
@@ -95,7 +95,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 coredisrl = in_be32(&gur->coredisrl);
 
 	return (coredisrl & (1 << nr));
@@ -103,7 +103,7 @@ int is_core_disabled(int nr) {
 #else
 int cpu_disable(u32 nr)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 	switch (nr) {
 	case 0:
@@ -121,7 +121,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 devdisr = in_be32(&gur->devdisr);
 
 	switch (nr) {
@@ -264,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	u32 mask = cpu_mask();
 	struct law_entry e;
 
-	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
 	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
-	pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+	pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
 	whoami = in_be32(&pic->whoami);
 	cpu_up_mask = 1 << whoami;
@@ -336,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	u32 up, cpu_up_mask, whoami;
 	u32 *table = (u32 *)&__spin_table;
 	volatile u32 bpcr;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 	u32 devdisr;
 	int timeout = 10;
 
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 111692f..cbcb57f 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
+	void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
 	u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
 	u32 srds1_io_sel, srds2_io_sel;
 	u32 tmp;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index f3b5450..a48f3c1 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -52,7 +52,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 38f30af..479ee08 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -32,7 +32,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index 8cba422..56e5ef6 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -51,7 +51,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 6b8e447..47f13e3 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -50,8 +50,8 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+	serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
 
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index bf5cac6..7a8f653 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index f36b1b6..8c5d82a 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 pordevsr = in_be32(&gur->pordevsr);
 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index c5b1443..3cf41ca 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_2bit_assign;
 	u32			pin_1bit_mask;
 	u32			tmp_val;
-	volatile ccsr_gur_t	*gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t	*gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	volatile par_io_t	*par_io = (volatile par_io_t *)
 						&(gur->qe_par_io);
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 6686b7c..a7004a6 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(sys_info_t *sys_info)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -575,7 +575,7 @@ int get_clocks(void)
 {
 	sys_info_t sys_info;
 #ifdef CONFIG_ARCH_MPC8544
-	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
 #endif
 	get_sys_info (&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index bdd7338..47df3c2 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 ulong cpu_init_f(void)
 {
 #ifdef CONFIG_SYS_INIT_L2_ADDR
-	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 
 	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9d44fa4..024414e 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,7 +80,7 @@
 
 /* Definitions from C header file asm/immap_85xx.h */
 
-#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CFG_SYS_MPC85xx_L2_OFFSET		0x20000
 
 #define MPC85xx_L2CTL				0x000
 #define MPC85xx_L2CTL_L2E			0x80000000
@@ -127,13 +127,13 @@ bootsect:
 	.org 0x80 /* Start of configuration */
 	.Lconf_pair_start:
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
 	.long CONFIG_SYS_INIT_L2_ADDR
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
 	.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
 
-	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
 	.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 97ed24a..8f451b4 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -260,7 +260,7 @@ void UnknownException(struct pt_regs *regs)
 
 void ExtIntException(struct pt_regs *regs)
 {
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
 	uint vect;
 
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 0985fb2..7f20190 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = {
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 static inline u32 init_type(u32 cluster, int init_id)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 	u32 type = in_be32(&gur->tp_ityp[idx]);
 
@@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)
 
 u32 compute_ppc_cpumask(void)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type, mask = 0;
 
@@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void)
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 u32 compute_dsp_cpumask(void)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	int i = CONFIG_DSP_CLUSTER_START, count = 0;
 	u32 cluster, type, dsp_mask = 0;
 
@@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)
 
 int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	int count = 0, i = CONFIG_DSP_CLUSTER_START;
 	u32 cluster;
 
@@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster;
 
@@ -235,7 +235,7 @@ struct cpu_type *identify_cpu(u32 ver)
  */
 __weak u32 cpu_mask(void)
 {
-	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+	ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
 	struct cpu_type *cpu = gd->arch.cpu;
 
 	/* better to query feature reporting register than just assume 1 */
@@ -252,7 +252,7 @@ __weak u32 cpu_mask(void)
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 __weak u32 cpu_dsp_mask(void)
 {
-	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+	ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
 	struct cpu_type *cpu = gd->arch.cpu;
 
 	/* better to query feature reporting register than just assume 1 */
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 24bbe3b..4e3f900 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -301,7 +301,7 @@ void init_laws(void)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 	/* check RCW to get which port is used for boot */
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 	u32 bootloc = in_be32(&gur->rcwsr[6]);
 	/*
 	 * in SRIO or PCIE boot we need to set specail LAWs for
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c73cf93..62524a2 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -33,12 +33,12 @@
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
 #endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
-	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
 	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
 	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
 	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
-	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC86xx)
 	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
 	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 7ced50c..be55f99 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,15 +18,15 @@ struct srio_liodn_id_table {
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
 	SET_LIODN_ENTRY_1(compat, liodn, \
-		offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+		offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
 		compatoff)
 
 #define SET_USB_LIODN(usbNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
-		CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+		CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
 
 #define SET_SATA_LIODN(sataNum, liodn) \
 	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
-		CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+		CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
 
 #define SET_PCI_LIODN(compat, pciNum, liodn) \
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
-		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 #define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
 	SET_LIODN_ENTRY_1(compat, liodn,\
-		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
-		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
-		CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+		CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
 
 #define SET_SDHC_LIODN(sdhcNum, liodn) \
 	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
-		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+		CFG_SYS_MPC85xx_ESDHC_OFFSET)
 
 #define SET_QE_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
-		CONFIG_SYS_MPC85xx_QE_OFFSET)
+		CFG_SYS_MPC85xx_QE_OFFSET)
 
 #define SET_TDM_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
-		CONFIG_SYS_MPC85xx_TDM_OFFSET)
+		CFG_SYS_MPC85xx_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index c731347..0bf5b9c 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -861,15 +861,15 @@ struct ccsr_gpio {
 	};
 };
 
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
+#define CFG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
+#define CFG_SYS_MPC83xx_DMA_ADDR \
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
+#define CFG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
+#define CFG_SYS_MPC83xx_ESDHC_ADDR \
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
 
 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7e88779..7a7a7f2 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2437,9 +2437,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
 #endif
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x8000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
-#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET		0x8000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
+#define CFG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
@@ -2457,36 +2457,36 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
-#define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
-#define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
-#define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
-#define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
-#define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
+#define CFG_SYS_MPC85xx_DMA1_OFFSET		0x100000
+#define CFG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CFG_SYS_MPC85xx_DMA3_OFFSET		0x102000
+#define CFG_SYS_MPC85xx_DMA_OFFSET		CFG_SYS_MPC85xx_DMA1_OFFSET
+#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x110000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
+#define CFG_SYS_MPC85xx_LBC_OFFSET		0x124000
+#define CFG_SYS_MPC85xx_IFC_OFFSET		0x124000
+#define CFG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CFG_SYS_MPC85xx_TDM_OFFSET		0x185000
+#define CFG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
 	!defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
 #endif
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
+#define CFG_SYS_MPC85xx_USB1_OFFSET		0x210000
+#define CFG_SYS_MPC85xx_USB2_OFFSET		0x211000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x220000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
 #define CONFIG_SYS_SEC_MON_OFFSET		0x314000
@@ -2515,32 +2515,32 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x2000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
-#define CONFIG_SYS_MPC85xx_PCI1_OFFSET		0x8000
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
-#define CONFIG_SYS_MPC85xx_PCI2_OFFSET		0x9000
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
+#define CFG_SYS_MPC85xx_ECM_OFFSET		0x0000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET		0x2000
+#define CFG_SYS_MPC85xx_LBC_OFFSET		0x5000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
+#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x7000
+#define CFG_SYS_MPC85xx_PCI1_OFFSET		0x8000
+#define CFG_SYS_MPC85xx_PCIX_OFFSET		0x8000
+#define CFG_SYS_MPC85xx_PCI2_OFFSET		0x9000
+#define CFG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
 #endif
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
-#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
+#define CFG_SYS_MPC85xx_GPIO_OFFSET		0xF000
+#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x18000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x19000
+#define CFG_SYS_MPC85xx_IFC_OFFSET		0x1e000
+#define CFG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CFG_SYS_MPC85xx_DMA_OFFSET		0x21000
+#define CFG_SYS_MPC85xx_USB1_OFFSET		0x22000
+#define CFG_SYS_MPC85xx_USB2_OFFSET		0x23000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
@@ -2549,7 +2549,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
@@ -2557,8 +2557,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
+#define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
@@ -2569,8 +2569,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
+#define CFG_SYS_MPC85xx_PIC_OFFSET		0x40000
+#define CFG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
@@ -2587,50 +2587,50 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_MPC85xx_GUTS_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_MPC85xx_ECM_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_FSL_DDR2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_FSL_DDR3_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
+#define CFG_SYS_MPC85xx_ESPI_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CFG_SYS_MPC85xx_GPIO_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
+#define CFG_SYS_MPC85xx_SATA1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
+#define CFG_SYS_MPC85xx_SATA2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
+#define CFG_SYS_MPC85xx_L2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
+#define CFG_SYS_MPC85xx_DMA_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
+#define CFG_SYS_MPC85xx_ESDHC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_PIC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
@@ -2639,14 +2639,14 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
@@ -2663,17 +2663,17 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
 #define CONFIG_SYS_PCI2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
 #define CONFIG_SYS_PCIE1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
 #define CONFIG_SYS_PCIE2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
 #define CONFIG_SYS_PCIE4_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
 
 #define CONFIG_SYS_SFP_ADDR  \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
@@ -2752,9 +2752,9 @@ struct dcsr_dcfg_regs {
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 
-#define CONFIG_SYS_MPC85xx_SCFG \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
-#define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+#define CFG_SYS_MPC85xx_SCFG \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
+#define CFG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
 /* The supplement configuration unit register */
 struct ccsr_scfg {
 	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index feebe15..0ed6bec 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
 		unsigned int dir, unsigned int val)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* First mask off the unwanted parts of "dir" and "val" */
 	dir &= mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* Read the requested values */
 	return in_be32(&gpio->gpdat) & mask;