powerpc, 8260: remove support for mpc8260

There was for long time no activity in the 8260 area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8260,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

7 files changed, 1 insertions, 1743 deletions

diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
deleted file mode 100644
index 4f78186..0000000
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/*
- * MPC8260 Communication Processor Module.
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the MPC8260 internal
- * memory map.  See immap.h for details.
- */
-#ifndef __CPM_82XX__
-#define __CPM_82XX__
-
-#include <asm/immap_8260.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((uint)0x80000000)
-#define CPM_CR_PAGE	((uint)0x7c000000)
-#define CPM_CR_SBLOCK	((uint)0x03e00000)
-#define CPM_CR_FLG	((uint)0x00010000)
-#define CPM_CR_MCN	((uint)0x00003fc0)
-#define CPM_CR_OPCODE	((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK	(0x04)
-#define CPM_CR_SCC2_SBLOCK	(0x05)
-#define CPM_CR_SCC3_SBLOCK	(0x06)
-#define CPM_CR_SCC4_SBLOCK	(0x07)
-#define CPM_CR_SMC1_SBLOCK	(0x08)
-#define CPM_CR_SMC2_SBLOCK	(0x09)
-#define CPM_CR_SPI_SBLOCK	(0x0a)
-#define CPM_CR_I2C_SBLOCK	(0x0b)
-#define CPM_CR_TIMER_SBLOCK	(0x0f)
-#define CPM_CR_RAND_SBLOCK	(0x0e)
-#define CPM_CR_FCC1_SBLOCK	(0x10)
-#define CPM_CR_FCC2_SBLOCK	(0x11)
-#define CPM_CR_FCC3_SBLOCK	(0x12)
-#define CPM_CR_IDMA1_SBLOCK	(0x14)
-#define CPM_CR_IDMA2_SBLOCK	(0x15)
-#define CPM_CR_IDMA3_SBLOCK	(0x16)
-#define CPM_CR_IDMA4_SBLOCK	(0x17)
-#define CPM_CR_MCC1_SBLOCK	(0x1c)
-
-#define CPM_CR_SCC1_PAGE	(0x00)
-#define CPM_CR_SCC2_PAGE	(0x01)
-#define CPM_CR_SCC3_PAGE	(0x02)
-#define CPM_CR_SCC4_PAGE	(0x03)
-#define CPM_CR_SMC1_PAGE	(0x07)
-#define CPM_CR_SMC2_PAGE	(0x08)
-#define CPM_CR_SPI_PAGE		(0x09)
-#define CPM_CR_I2C_PAGE		(0x0a)
-#define CPM_CR_TIMER_PAGE	(0x0a)
-#define CPM_CR_RAND_PAGE	(0x0a)
-#define CPM_CR_FCC1_PAGE	(0x04)
-#define CPM_CR_FCC2_PAGE	(0x05)
-#define CPM_CR_FCC3_PAGE	(0x06)
-#define CPM_CR_IDMA1_PAGE	(0x07)
-#define CPM_CR_IDMA2_PAGE	(0x08)
-#define CPM_CR_IDMA3_PAGE	(0x09)
-#define CPM_CR_IDMA4_PAGE	(0x0a)
-#define CPM_CR_MCC1_PAGE	(0x07)
-#define CPM_CR_MCC2_PAGE	(0x08)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE	((uint)128)
-#define CPM_DP_NOSPACE		((uint)0x7fffffff)
-#ifndef CONFIG_MPC8272_FAMILY
-#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x0000b000)
-#else  /* 8247/48/71/72 */
-#define CPM_DATAONLY_SIZE	((uint)(4 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
-#endif /* !CONFIG_MPC8272_FAMILY */
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES	2
-
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern	cpm8260_t	*cpmp;		/* Pointer to comm processor */
-uint		m8260_cpm_dpalloc(uint size, uint align);
-uint		m8260_cpm_hostalloc(uint size, uint align);
-void		m8260_cpm_setbrg(uint brg, uint rate);
-void		m8260_cpm_fastbrg(uint brg, uint rate, int div16);
-void		m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_CD	((ushort)0x0001)	/* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
-#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
-#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
-#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
-#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
-#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
-#else
-#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
-#endif
-
-#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
-#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
-#else
-#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
-#endif
-
-#define PROFF_SCC1		((uint)0x8000)
-#define PROFF_SCC2		((uint)0x8100)
-#define PROFF_SCC3		((uint)0x8200)
-#define PROFF_SCC4		((uint)0x8300)
-#define PROFF_FCC1		((uint)0x8400)
-#define PROFF_FCC2		((uint)0x8500)
-#define PROFF_FCC3		((uint)0x8600)
-#define PROFF_MCC1		((uint)0x8700)
-#define PROFF_SMC1_BASE		((uint)0x87fc)
-#define PROFF_IDMA1_BASE	((uint)0x87fe)
-#define PROFF_MCC2		((uint)0x8800)
-#define PROFF_SMC2_BASE		((uint)0x88fc)
-#define PROFF_IDMA2_BASE	((uint)0x88fe)
-#define PROFF_SPI_BASE		((uint)0x89fc)
-#define PROFF_IDMA3_BASE	((uint)0x89fe)
-#define PROFF_TIMERS		((uint)0x8ae0)
-#define PROFF_REVNUM		((uint)0x8af0)
-#define PROFF_RAND		((uint)0x8af8)
-#define PROFF_I2C_BASE		((uint)0x8afc)
-#define PROFF_IDMA4_BASE	((uint)0x8afe)
-
-/* The SMCs are relocated to any of the first eight DPRAM pages.
- * We will fix these at the first locations of DPRAM, until we
- * get some microcode patches :-).
- * The parameter ram space for the SMCs is fifty-some bytes, and
- * they are required to start on a 64 byte boundary.
- */
-#define PROFF_SMC1	(0)
-#define PROFF_SMC2	(64)
-#define PROFF_SPI	((16*1024) - 128)
-
-/* Define enough so I can at least use the serial port as a UART.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	uint	smc_stmp;	/* SDMA Temp */
-} smc_uart_t;
-
-/* SMC uart mode register (Internal memory map).
-*/
-#define	SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC Event and Mask register.
-*/
-#define	SMCM_TXE	((unsigned char)0x10)
-#define	SMCM_BSY	((unsigned char)0x04)
-#define	SMCM_TX		((unsigned char)0x02)
-#define	SMCM_RX		((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define	SCCM_TXE	((unsigned char)0x10)
-#define	SCCM_BSY	((unsigned char)0x04)
-#define	SCCM_TX		((unsigned char)0x02)
-#define	SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY	((ushort)0x8000)
-#define BD_ENET_RX_WRAP		((ushort)0x2000)
-#define BD_ENET_RX_INTR		((ushort)0x1000)
-#define BD_ENET_RX_LAST		((ushort)0x0800)
-#define BD_ENET_RX_FIRST	((ushort)0x0400)
-#define BD_ENET_RX_MISS		((ushort)0x0100)
-#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
-#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
-#define BD_ENET_RX_LG		((ushort)0x0020)
-#define BD_ENET_RX_NO		((ushort)0x0010)
-#define BD_ENET_RX_SH		((ushort)0x0008)
-#define BD_ENET_RX_CR		((ushort)0x0004)
-#define BD_ENET_RX_OV		((ushort)0x0002)
-#define BD_ENET_RX_CL		((ushort)0x0001)
-#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY	((ushort)0x8000)
-#define BD_ENET_TX_PAD		((ushort)0x4000)
-#define BD_ENET_TX_WRAP		((ushort)0x2000)
-#define BD_ENET_TX_INTR		((ushort)0x1000)
-#define BD_ENET_TX_LAST		((ushort)0x0800)
-#define BD_ENET_TX_TC		((ushort)0x0400)
-#define BD_ENET_TX_DEF		((ushort)0x0200)
-#define BD_ENET_TX_HB		((ushort)0x0100)
-#define BD_ENET_TX_LC		((ushort)0x0080)
-#define BD_ENET_TX_RL		((ushort)0x0040)
-#define BD_ENET_TX_RCMASK	((ushort)0x003c)
-#define BD_ENET_TX_UN		((ushort)0x0002)
-#define BD_ENET_TX_CSL		((ushort)0x0001)
-#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	uint	scc_res1;	/* Reserved */
-	uint	scc_res2;	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST		((ushort)0x0800)
-
-/*  SCC as HDLC controller - taken from commproc.h
- */
-typedef struct scc_hdlc {
-	sccp_t  sh_genscc;
-	/*
-	* HDLC specific parameter RAM
-	*/
-	uchar   res[4];         /* reserved */
-	ulong   sh_cmask;       /* CRC constant */
-	ulong   sh_cpres;       /* CRC preset */
-	ushort  sh_disfc;       /* discarded frame counter */
-	ushort  sh_crcec;       /* CRC error counter */
-	ushort  sh_abtsc;       /* abort sequence counter */
-	ushort  sh_nmarc;       /* nonmatching address rx cnt */
-	ushort  sh_retrc;       /* frame retransmission cnt */
-	ushort  sh_mflr;        /* maximum frame length reg */
-	ushort  sh_maxcnt;      /* maximum length counter */
-	ushort  sh_rfthr;       /* received frames threshold */
-	ushort  sh_rfcnt;       /* received frames count */
-	ushort  sh_hmask;       /* user defined frm addr mask */
-	ushort  sh_haddr1;      /* user defined frm address 1 */
-	ushort  sh_haddr2;      /* user defined frm address 2 */
-	ushort  sh_haddr3;      /* user defined frm address 3 */
-	ushort  sh_haddr4;      /* user defined frm address 4 */
-	ushort  tmp;            /* temp */
-	ushort  tmp_mb;         /* temp */
-} scc_hdlc_t;
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
-#define FCC_GFMR_TCI		((uint)0x20000000)
-#define FCC_GFMR_TRX		((uint)0x10000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_CDP		((uint)0x04000000)
-#define FCC_GFMR_CTSP		((uint)0x02000000)
-#define FCC_GFMR_CDS		((uint)0x01000000)
-#define FCC_GFMR_CTSS		((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
-#define FCC_GFMR_SYNL_8		((uint)0x00008000)
-#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
-#define FCC_GFMR_RTSM		((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
-#define FCC_GFMR_REVD		((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
-#define FCC_GFMR_TCRC_16	((uint)0x00000000)
-#define FCC_GFMR_TCRC_32	((uint)0x00000080)
-#define FCC_GFMR_ENR		((uint)0x00000020)
-#define FCC_GFMR_ENT		((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-	ushort	fcc_riptr;	/* Rx Internal temp pointer */
-	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
-	ushort	fcc_res1;
-	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
-	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_rbase;	/* Receive BD base */
-	ushort	fcc_rbdstat;	/* RxBD status */
-	ushort	fcc_rbdlen;	/* RxBD down counter */
-	uint	fcc_rdptr;	/* RxBD internal data pointer */
-	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_tbase;	/* Transmit BD base */
-	ushort	fcc_tbdstat;	/* TxBD status */
-	ushort	fcc_tbdlen;	/* TxBD down counter */
-	uint	fcc_tdptr;	/* TxBD internal data pointer */
-	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
-	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
-	uint	fcc_rcrc;	/* Rx temp CRC */
-	uint	fcc_res2;
-	uint	fcc_tcrc;	/* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-	fccp_t	fen_genfcc;
-	uint	fen_statbuf;	/* Internal status buffer */
-	uint	fen_camptr;	/* CAM address */
-	uint	fen_cmask;	/* Constant mask for CRC */
-	uint	fen_cpres;	/* Preset CRC */
-	uint	fen_crcec;	/* CRC Error counter */
-	uint	fen_alec;	/* alignment error counter */
-	uint	fen_disfc;	/* discard frame counter */
-	ushort	fen_retlim;	/* Retry limit */
-	ushort	fen_retcnt;	/* Retry counter */
-	ushort	fen_pper;	/* Persistence */
-	ushort	fen_boffcnt;	/* backoff counter */
-	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
-	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
-	ushort	fen_tfcstat;	/* out of sequence TxBD */
-	ushort	fen_tfclen;
-	uint	fen_tfcptr;
-	ushort	fen_mflr;	/* Maximum frame length (1518) */
-	ushort	fen_paddrh;	/* MAC address */
-	ushort	fen_paddrm;
-	ushort	fen_paddrl;
-	ushort	fen_ibdcount;	/* Internal BD counter */
-	ushort	fen_idbstart;	/* Internal BD start pointer */
-	ushort	fen_ibdend;	/* Internal BD end pointer */
-	ushort	fen_txlen;	/* Internal Tx frame length counter */
-	uint	fen_ibdbase[8]; /* Internal use */
-	uint	fen_iaddrh;	/* Individual address filter */
-	uint	fen_iaddrl;
-	ushort	fen_minflr;	/* Minimum frame length (64) */
-	ushort	fen_taddrh;	/* Filter transfer MAC address */
-	ushort	fen_taddrm;
-	ushort	fen_taddrl;
-	ushort	fen_padptr;	/* Pointer to pad byte buffer */
-	ushort	fen_cftype;	/* control frame type */
-	ushort	fen_cfrange;	/* control frame range */
-	ushort	fen_maxb;	/* maximum BD count */
-	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
-	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
-	ushort	fen_maxd;	/* internal max DMA count */
-	ushort	fen_dmacnt;	/* internal DMA counter */
-	uint	fen_octc;	/* Total octect counter */
-	uint	fen_colc;	/* Total collision counter */
-	uint	fen_broc;	/* Total broadcast packet counter */
-	uint	fen_mulc;	/* Total multicast packet count */
-	uint	fen_uspc;	/* Total packets < 64 bytes */
-	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
-	uint	fen_ospc;	/* Total packets > 1518 */
-	uint	fen_jbrc;	/* Total packets > 1518 with errors */
-	uint	fen_p64c;	/* Total packets == 64 bytes */
-	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
-	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
-	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
-	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
-	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
-	uint	fen_cambuf;	/* Internal CAM buffer poiner */
-	ushort	fen_rfthr;	/* Received frames threshold */
-	ushort	fen_rfcnt;	/* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
-#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
-#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
-#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
-#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
-#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
-#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
-#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
-#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
-#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
-#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
-#define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
-#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
-#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
-	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
-	u_char	spi_rfcr;	/* Rx function code */
-	u_char	spi_tfcr;	/* Tx function code */
-	ushort	spi_mrblr;	/* Max receive buffer length */
-	uint	spi_rstate;	/* Internal */
-	uint	spi_rdp;	/* Internal */
-	ushort	spi_rbptr;	/* Internal */
-	ushort	spi_rbc;	/* Internal */
-	uint	spi_rxtmp;	/* Internal */
-	uint	spi_tstate;	/* Internal */
-	uint	spi_tdp;	/* Internal */
-	ushort	spi_tbptr;	/* Internal */
-	ushort	spi_tbc;	/* Internal */
-	uint	spi_txtmp;	/* Internal */
-	uint	spi_res;	/* Tx temp. */
-	uint	spi_res1[4];	/* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
-#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
-#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
-#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
-#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
-#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
-#define SPMODE_EN	((ushort)0x0100)	/* Enable */
-#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
-#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
-
-#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)	((x) &0xF)
-
-/* SPI Event/Mask register.
-*/
-#define SPI_EMASK		0x37	/* Event Mask				*/
-#define SPI_MME			0x20	/* Multi-Master Error			*/
-#define SPI_TXE			0x10	/* Transmit Error			*/
-#define SPI_BSY			0x04	/* Busy					*/
-#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
-#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
-
-#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
-
-#define SPI_EB		((u_char)0x10)		/* big endian byte order */
-
-#define BD_IIC_START		((ushort)0x0400)
-
-#endif /* __CPM_82XX__ */
diff --git a/arch/powerpc/include/asm/immap_8260.h b/arch/powerpc/include/asm/immap_8260.h
deleted file mode 100644
index c7021a7..0000000
--- a/arch/powerpc/include/asm/immap_8260.h
+++ /dev/null
@@ -1,604 +0,0 @@
-/*
- * MPC8260 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map of the 8260.	 I don't know how generic
- * this will be, as I don't have any knowledge of the subsequent
- * parts at this time.	I copied this from the 8xx_immap.h.
- */
-#ifndef __IMMAP_82XX__
-#define __IMMAP_82XX__
-
-/* System configuration registers.
-*/
-typedef struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	char	res1[6];
-	ushort	sc_swsr;
-	char	res2[20];
-	uint	sc_bcr;
-	u_char	sc_ppc_acr;
-	char	res3[3];
-	uint	sc_ppc_alrh;
-	uint	sc_ppc_alrl;
-	u_char	sc_lcl_acr;
-	char	res4[3];
-	uint	sc_lcl_alrh;
-	uint	sc_lcl_alrl;
-	uint	sc_tescr1;
-	uint	sc_tescr2;
-	uint	sc_ltescr1;
-	uint	sc_ltescr2;
-	uint	sc_pdtea;
-	u_char	sc_pdtem;
-	char	res5[3];
-	uint	sc_ldtea;
-	u_char	sc_ldtem;
-	char	res6[163];
-} sysconf8260_t;
-
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	uint	memc_br8;
-	uint	memc_or8;
-	uint	memc_br9;
-	uint	memc_or9;
-	uint	memc_br10;
-	uint	memc_or10;
-	uint	memc_br11;
-	uint	memc_or11;
-	char	res1[8];
-	uint	memc_mar;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	uint	memc_mcmr;
-	char	res3[8];
-	ushort	memc_mptpr;
-	char	res4[2];
-	uint	memc_mdr;
-	char	res5[4];
-	uint	memc_psdmr;
-	uint	memc_lsdmr;
-	u_char	memc_purt;
-	char	res6[3];
-	u_char	memc_psrt;
-	char	res7[3];
-	u_char	memc_lurt;
-	char	res8[3];
-	u_char	memc_lsrt;
-	char	res9[3];
-	uint	memc_immr;
-	uint	memc_pcibr0;
-	uint	memc_pcibr1;
-	char	res10[16];
-	uint	memc_pcimsk0;
-	uint	memc_pcimsk1;
-	char	res11[52];
-} memctl8260_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	char	res1[32];
-	ushort	sit_tmcntsc;
-	char	res2[2];
-	uint	sit_tmcnt;
-	char	res3[4];
-	uint	sit_tmcntal;
-	char	res4[16];
-	ushort	sit_piscr;
-	char	res5[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res6[94];
-	char	res7[390];
-} sit8260_t;
-
-/* PCI
- */
-typedef struct pci_config {
-	uint	pci_omisr;
-	uint	pci_ominr;
-	char	res1[8];
-	uint	pci_ifqpr;
-	uint	pci_ofqpr;
-	char	res2[8];
-	uint	pci_imr0;
-	uint	pci_imr1;
-	uint	pci_omr0;
-	uint	pci_omr1;
-	uint	pci_odr;
-	char	res3[4];
-	uint	pci_idr;
-	char	res4[20];
-	uint	pci_imisr;
-	uint	pci_imimr;
-	char	res5[24];
-	uint	pci_ifhpr;
-	char	res5_2[4];
-	uint	pci_iftpr;
-	char	res6[4];
-	uint	pci_iphpr;
-	char	res6_2[4];
-	uint	pci_iptpr;
-	char	res7[4];
-	uint	pci_ofhpr;
-	char	res7_2[4];
-	uint	pci_oftpr;
-	char	res8[4];
-	uint	pci_ophpr;
-	char	res8_2[4];
-	uint	pci_optpr;
-	char	res9[8];
-	uint	pci_mucr;
-	char	res10[8];
-	uint	pci_qbar;
-	char	res11[12];
-	uint	pci_dmamr0;
-	uint	pci_dmasr0;
-	uint	pci_dmacdar0;
-	char	res12[4];
-	uint	pci_dmasar0;
-	char	res13[4];
-	uint	pci_dmadar0;
-	char	res14[4];
-	uint	pci_dmabcr0;
-	uint	pci_dmandar0;
-	char	res15[88];
-	uint	pci_dmamr1;
-	uint	pci_dmasr1;
-	uint	pci_dmacdar1;
-	char	res16[4];
-	uint	pci_dmasar1;
-	char	res17[4];
-	uint	pci_dmadar1;
-	char	res18[4];
-	uint	pci_dmabcr1;
-	uint	pci_dmandar1;
-	char	res19[88];
-	uint	pci_dmamr2;
-	uint	pci_dmasr2;
-	uint	pci_dmacdar2;
-	char	res20[4];
-	uint	pci_dmasar2;
-	char	res21[4];
-	uint	pci_dmadar2;
-	char	res22[4];
-	uint	pci_dmabcr2;
-	uint	pci_dmandar2;
-	char	res23[88];
-	uint	pci_dmamr3;
-	uint	pci_dmasr3;
-	uint	pci_dmacdar3;
-	char	res24[4];
-	uint	pci_dmasar3;
-	char	res25[4];
-	uint	pci_dmadar3;
-	char	res26[4];
-	uint	pci_dmabcr3;
-	uint	pci_dmandar3;
-	char	res27[344];
-	uint	pci_potar0;
-	char	res28[4];
-	uint	pci_pobar0;
-	char	res29[4];
-	uint	pci_pocmr0;
-	char	res30[4];
-	uint	pci_potar1;
-	char	res31[4];
-	uint	pci_pobar1;
-	char	res32[4];
-	uint	pci_pocmr1;
-	char	res33[4];
-	uint	pci_potar2;
-	char	res34[4];
-	uint	pci_pobar2;
-	char	res35[4];
-	uint	pci_pocmr2;
-	char	res36[52];
-	uint	pci_ptcr;
-	uint	pci_gpcr;
-	uint	pci_gcr;
-	uint	pci_esr;
-	uint	pci_emr;
-	uint	pci_ecr;
-	uint	pci_eacr;
-	char	res37[4];
-	uint	pci_edcr;
-	char	res38[4];
-	uint	pci_eccr;
-	char	res39[44];
-	uint	pci_pitar1;
-	char	res40[4];
-	uint	pci_pibar1;
-	char	res41[4];
-	uint	pci_picmr1;
-	char	res42[4];
-	uint	pci_pitar0;
-	char	res43[4];
-	uint	pci_pibar0;
-	char	res44[4];
-	uint	pci_picmr0;
-	char	res45[4];
-	uint	pci_cfg_addr;
-	uint	pci_cfg_data;
-	uint	pci_int_ack;
-	char	res46[756];
-}pci8260_t;
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-	ushort	ic_sicr;
-	char	res1[2];
-	uint	ic_sivec;
-	uint	ic_sipnrh;
-	uint	ic_sipnrl;
-	uint	ic_siprr;
-	uint	ic_scprrh;
-	uint	ic_scprrl;
-	uint	ic_simrh;
-	uint	ic_simrl;
-	uint	ic_siexr;
-	char	res2[88];
-} intctl8260_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	char	res1[4];
-	uint	car_scmr;
-	char	res2[4];
-	uint	car_rsr;
-	uint	car_rmr;
-	char	res[104];
-} car8260_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-	uint	iop_pdira;
-	uint	iop_ppara;
-	uint	iop_psora;
-	uint	iop_podra;
-	uint	iop_pdata;
-	char	res1[12];
-	uint	iop_pdirb;
-	uint	iop_pparb;
-	uint	iop_psorb;
-	uint	iop_podrb;
-	uint	iop_pdatb;
-	char	res2[12];
-	uint	iop_pdirc;
-	uint	iop_pparc;
-	uint	iop_psorc;
-	uint	iop_podrc;
-	uint	iop_pdatc;
-	char	res3[12];
-	uint	iop_pdird;
-	uint	iop_ppard;
-	uint	iop_psord;
-	uint	iop_podrd;
-	uint	iop_pdatd;
-	char	res4[12];
-} iop8260_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	u_char	cpmt_tgcr1;
-	char	res1[3];
-	u_char	cpmt_tgcr2;
-	char	res2[11];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res3[584];
-} cpmtimer8260_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res0[24];
-	u_char	sdma_sdsr;
-	char	res1[3];
-	u_char	sdma_sdmr;
-	char	res2[3];
-	u_char	sdma_idsr1;
-	char	res3[3];
-	u_char	sdma_idmr1;
-	char	res4[3];
-	u_char	sdma_idsr2;
-	char	res5[3];
-	u_char	sdma_idmr2;
-	char	res6[3];
-	u_char	sdma_idsr3;
-	char	res7[3];
-	u_char	sdma_idmr3;
-	char	res8[3];
-	u_char	sdma_idsr4;
-	char	res9[3];
-	u_char	sdma_idmr4;
-	char	res10[707];
-} sdma8260_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-	uint	fcc_gfmr;
-	uint	fcc_fpsmr;
-	ushort	fcc_ftodr;
-	char	res1[2];
-	ushort	fcc_fdsr;
-	char	res2[2];
-	ushort	fcc_fcce;
-	char	res3[2];
-	ushort	fcc_fccm;
-	char	res4[2];
-	u_char	fcc_fccs;
-	char	res5[3];
-	u_char	fcc_ftirr_phy[4];
-} fcc_t;
-
-/* Fast controllers continued
- */
-typedef struct fcc_c {
-	uint	fcc_firper;
-	uint	fcc_firer;
-	uint	fcc_firsr_hi;
-	uint	fcc_firsr_lo;
-	u_char	fcc_gfemr;
-	char	res1[15];
-} fcc_c_t;
-
-/* TC Layer
- */
-typedef struct tclayer {
-	ushort	tc_tcmode;
-	ushort	tc_cdsmr;
-	ushort	tc_tcer;
-	ushort	tc_rcc;
-	ushort	tc_tcmr;
-	ushort	tc_fcc;
-	ushort	tc_ccc;
-	ushort	tc_icc;
-	ushort	tc_tcc;
-	ushort	tc_ecc;
-	char	res1[12];
-} tclayer_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[331];
-} i2c8260_t;
-
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_psmr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct im_spi {
-	ushort	spi_spmode;
-	char	res1[4];
-	u_char	spi_spie;
-	char	res2[3];
-	u_char	spi_spim;
-	char	res3[2];
-	u_char	spi_spcom;
-	char	res4[82];
-} im_spi_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-	u_char	cmx_si1cr;
-	char	res1;
-	u_char	cmx_si2cr;
-	char	res2;
-	uint	cmx_fcr;
-	uint	cmx_scr;
-	u_char	cmx_smr;
-	char	res3;
-	ushort	cmx_uar;
-	char	res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-	ushort	si_amr;
-	ushort	si_bmr;
-	ushort	si_cmr;
-	ushort	si_dmr;
-	u_char	si_gmr;
-	char	res1;
-	u_char	si_cmdr;
-	char	res2;
-	u_char	si_str;
-	char	res3;
-	ushort	si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-	ushort	mcc_mcce;
-	char	res1[2];
-	ushort	mcc_mccm;
-	char	res2[2];
-	u_char	mcc_mccf;
-	char	res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-	uint	cp_cpcr;
-	uint	cp_rccr;
-	char	res1[14];
-	ushort	cp_rter;
-	char	res2[2];
-	ushort	cp_rtmr;
-	ushort	cp_rtscr;
-	char	res3[2];
-	uint	cp_rtsr;
-	char	res4[12];
-} cpm8260_t;
-
-/* ...and the whole thing wrapped up....
-*/
-typedef struct immap {
-	/* Some references are into the unique and known dpram spaces,
-	 * others are from the generic base.
-	 */
-	union {
-		struct {
-			u_char		im_dpram1[16 * 1024];
-			char		res1[16 * 1024];
-			u_char		im_dpram2[4 * 1024];
-			char		res2[8 * 1024];
-			u_char		im_dpram3[4 * 1024];
-			char		res3[16 * 1024];
-		};
-		u8	im_dprambase[64 * 1024];
-		u16	im_dprambase16[32 * 1024];
-	};
-
-	sysconf8260_t	im_siu_conf;	/* SIU Configuration */
-	memctl8260_t	im_memctl;	/* Memory Controller */
-	sit8260_t	im_sit;		/* System Integration Timers */
-	pci8260_t	im_pci;		/* PCI Configuration */
-	intctl8260_t	im_intctl;	/* Interrupt Controller */
-	car8260_t	im_clkrst;	/* Clocks and reset */
-	iop8260_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8260_t	im_cpmtimer;	/* CPM timers */
-	sdma8260_t	im_sdma;	/* SDMA control/status */
-
-	fcc_t		im_fcc[3];	/* Three FCCs */
-
-	char		res4[32];
-	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
-	char		res4a[32];
-
-	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
-	ushort		tc_tcgsr;
-	ushort		tc_tcger;
-
-	/* First set of baud rate generators.
-	*/
-	char		res4b[236];
-	uint		im_brgc5;
-	uint		im_brgc6;
-	uint		im_brgc7;
-	uint		im_brgc8;
-
-	char		res5[608];
-
-	i2c8260_t	im_i2c;		/* I2C control/status */
-	cpm8260_t	im_cpm;		/* Communication processor */
-
-	/* Second set of baud rate generators.
-	*/
-	uint		im_brgc1;
-	uint		im_brgc2;
-	uint		im_brgc3;
-	uint		im_brgc4;
-
-	scc_t		im_scc[4];	/* Four SCCs */
-	smc_t		im_smc[2];	/* Couple of SMCs */
-	im_spi_t	im_spi;		/* A SPI */
-	cpmux_t		im_cpmux;	/* CPM clock route mux */
-	siramctl_t	im_siramctl1;	/* First SI RAM Control */
-	mcc_t		im_mcc1;	/* First MCC */
-	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
-	mcc_t		im_mcc2;	/* Second MCC */
-
-	char		res6[1184];
-
-	ushort		im_si1txram[256];
-	char		res7[512];
-	ushort		im_si1rxram[256];
-	char		res8[512];
-	ushort		im_si2txram[256];
-	char		res9[512];
-	ushort		im_si2rxram[256];
-	char		res10[512];
-	char		res11[4096];
-} immap_t;
-
-#endif /* __IMMAP_82XX__ */
diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h
deleted file mode 100644
index 617584d..0000000
--- a/arch/powerpc/include/asm/iopin_8260.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * MPC8260 I/O port pin manipulation functions
- */
-
-#ifndef _ASM_IOPIN_8260_H_
-#define _ASM_IOPIN_8260_H_
-
-#include <linux/types.h>
-#include <asm/immap_8260.h>
-
-#ifdef __KERNEL__
-
-typedef
-    struct {
-	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
-	u_char pin:5;	/* port pin (0-31) */
-	u_char flag:1;	/* for whatever */
-    }
-iopin_t;
-
-#define IOPIN_PORTA	0
-#define IOPIN_PORTB	1
-#define IOPIN_PORTC	2
-#define IOPIN_PORTD	3
-
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
-{
-    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
-    return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
-{
-    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
-    return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
-{
-    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
-    return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
-{
-    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
-    return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
-{
-    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
-    return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_8260_H_ */
diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h
deleted file mode 100644
index 6daca4f..0000000
--- a/arch/powerpc/include/asm/m8260_pci.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#define M8265_PCIBR0	0x101ac
-#define M8265_PCIBR1	0x101b0
-#define M8265_PCIMSK0	0x101c4
-#define M8265_PCIMSK1	0x101c8
-
-/* Bit definitions for PCIBR registers */
-
-#define PCIBR_ENABLE        0x00000001
-
-/* Bit definitions for PCIMSK registers */
-
-#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
-#define PCIMSK_64KB         0xFFFF0000
-#define PCIMSK_128KB        0xFFFE0000
-#define PCIMSK_256KB        0xFFFC0000
-#define PCIMSK_512KB        0xFFF80000
-#define PCIMSK_1MB          0xFFF00000
-#define PCIMSK_2MB          0xFFE00000
-#define PCIMSK_4MB          0xFFC00000
-#define PCIMSK_8MB          0xFF800000
-#define PCIMSK_16MB         0xFF000000
-#define PCIMSK_32MB         0xFE000000
-#define PCIMSK_64MB         0xFC000000
-#define PCIMSK_128MB        0xF8000000
-#define PCIMSK_256MB        0xF0000000
-#define PCIMSK_512MB        0xE0000000
-#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
-
-
-#define M826X_SCCR_PCI_MODE_EN 0x100
-
-
-/*
- * Outbound ATU registers (3 sets). These registers control how 60x bus (local)
- * addresses are translated to PCI addresses when the MPC826x is a PCI bus
- * master (initiator).
- */
-
-#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
-#define POTAR_REG1          0x10818
-#define POTAR_REG2          0x10830
-
-#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
-#define POBAR_REG1          0x10820
-#define POBAR_REG2          0x10838
-
-#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
-#define POCMR_REG1          0x10828
-#define POCMR_REG2          0x10840
-
-/* Bit definitions for POMCR registers */
-
-#define POCMR_MASK_4KB      0x000FFFFF
-#define POCMR_MASK_8KB      0x000FFFFE
-#define POCMR_MASK_16KB     0x000FFFFC
-#define POCMR_MASK_32KB     0x000FFFF8
-#define POCMR_MASK_64KB     0x000FFFF0
-#define POCMR_MASK_128KB    0x000FFFE0
-#define POCMR_MASK_256KB    0x000FFFC0
-#define POCMR_MASK_512KB    0x000FFF80
-#define POCMR_MASK_1MB      0x000FFF00
-#define POCMR_MASK_2MB      0x000FFE00
-#define POCMR_MASK_4MB      0x000FFC00
-#define POCMR_MASK_8MB      0x000FF800
-#define POCMR_MASK_16MB     0x000FF000
-#define POCMR_MASK_32MB     0x000FE000
-#define POCMR_MASK_64MB     0x000FC000
-#define POCMR_MASK_128MB    0x000F8000
-#define POCMR_MASK_256MB    0x000F0000
-#define POCMR_MASK_512MB    0x000E0000
-#define POCMR_MASK_1GB      0x000C0000
-
-#define POCMR_ENABLE        0x80000000
-#define POCMR_PCI_IO        0x40000000
-#define POCMR_PREFETCH_EN   0x20000000
-
-/* Soft PCI reset */
-
-#define PCI_GCR_REG         0x10880
-
-/* Bit definitions for PCI_GCR registers */
-
-#define PCIGCR_PCI_BUS_EN   0x1
-
-/*
- * Inbound ATU registers (2 sets). These registers control how PCI addresses
- * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
- */
-
-#define PITAR_REG1          0x108D0
-#define PIBAR_REG1          0x108D8
-#define PICMR_REG1          0x108E0
-#define PITAR_REG0          0x108E8
-#define PIBAR_REG0          0x108F0
-#define PICMR_REG0          0x108F8
-
-/* Bit definitions for PCI Inbound Comparison Mask registers */
-
-#define PICMR_MASK_4KB       0x000FFFFF
-#define PICMR_MASK_8KB       0x000FFFFE
-#define PICMR_MASK_16KB      0x000FFFFC
-#define PICMR_MASK_32KB      0x000FFFF8
-#define PICMR_MASK_64KB      0x000FFFF0
-#define PICMR_MASK_128KB     0x000FFFE0
-#define PICMR_MASK_256KB     0x000FFFC0
-#define PICMR_MASK_512KB     0x000FFF80
-#define PICMR_MASK_1MB       0x000FFF00
-#define PICMR_MASK_2MB       0x000FFE00
-#define PICMR_MASK_4MB       0x000FFC00
-#define PICMR_MASK_8MB       0x000FF800
-#define PICMR_MASK_16MB      0x000FF000
-#define PICMR_MASK_32MB      0x000FE000
-#define PICMR_MASK_64MB      0x000FC000
-#define PICMR_MASK_128MB     0x000F8000
-#define PICMR_MASK_256MB     0x000F0000
-#define PICMR_MASK_512MB     0x000E0000
-#define PICMR_MASK_1GB       0x000C0000
-
-#define PICMR_ENABLE         0x80000000
-#define PICMR_NO_SNOOP_EN    0x40000000
-#define PICMR_PREFETCH_EN    0x20000000
-
-/* PCI error Registers */
-
-#define	PCI_ERROR_STATUS_REG		0x10884
-#define	PCI_ERROR_MASK_REG		0x10888
-#define	PCI_ERROR_CONTROL_REG		0x1088C
-#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
-#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
-#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
-
-/* PCI error Register bit defines */
-
-#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
-#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
-#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
-#define	PCI_ERROR_PCI_NO_RSP			0x00000008
-#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
-#define	PCI_ERROR_PCI_SERR			0x00000020
-#define	PCI_ERROR_PCI_PERR_RD			0x00000040
-#define	PCI_ERROR_PCI_PERR_WR			0x00000080
-#define	PCI_ERROR_I2O_OFQO			0x00000100
-#define	PCI_ERROR_I2O_IPQO			0x00000200
-#define	PCI_ERROR_IRA				0x00000400
-#define	PCI_ERROR_NMI				0x00000800
-#define	PCI_ERROR_I2O_DBMC			0x00001000
-
-/*
- * Register pair used to generate configuration cycles on the PCI bus
- * and access the MPC826x's own PCI configuration registers.
- */
-
-#define PCI_CFG_ADDR_REG     0x10900
-#define PCI_CFG_DATA_REG     0x10904
-
-/* Bus parking decides where the bus control sits when idle */
-/* If modifying memory controllers for PCI park on the core */
-
-#define PPC_ACR_BUS_PARK_CORE 0x6
-#define PPC_ACR_BUS_PARK_PCI  0x3
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 8abe727..f23ed3e 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -19,11 +19,6 @@
 #include <mpc5xxx.h>
 #elif defined(CONFIG_MPC512X)
 #include <asm/immap_512x.h>
-#elif defined(CONFIG_MPC8260)
-#if defined(CONFIG_MPC8247) || defined(CONFIG_MPC8272)
-#define CONFIG_MPC8272_FAMILY	1
-#endif
-#include <asm/immap_8260.h>
 #endif
 #ifdef CONFIG_MPC86xx
 #include <mpc86xx.h>
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index aaabae0..6549a09 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1364,9 +1364,6 @@ int prt_8260_clks(void);
 #if defined(CONFIG_WALNUT)
 #define _machine _MACH_walnut
 #define have_of 0
-#elif defined(CONFIG_MPC8260)
-#define _machine _MACH_8260
-#define have_of 0
 #else
 #error "Machine not defined correctly"
 #endif
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
index c151b54..2767c05 100644
--- a/arch/powerpc/include/asm/status_led.h
+++ b/arch/powerpc/include/asm/status_led.h
@@ -9,9 +9,7 @@
 
 /* if not overridden */
 #ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC
-# if defined(CONFIG_MPC8260)
-#  include <mpc8260.h>
-# elif defined(CONFIG_5xx)
+# if defined(CONFIG_5xx)
 #  include <mpc5xx.h>
 # else
 #  error CPU specific Status LED header file missing.