diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:08 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:15 -0500 |
| commit | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 (patch) | |
| tree | 0fa435d86fef19ff6a83eedcc6c1c1f26527f8c5 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 69c7826759a69456df2a47fa4ef5dde19ab87e62 (diff) | |
| download | u-boot-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.zip u-boot-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.tar.gz u-boot-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.tar.bz2 | |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 8662ae4..23a3aaf 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -183,13 +183,6 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 -#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) - /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ - slwi r8,r4,1 - addi r8,r8,32 - mtspr L1CSR2,r8 -#endif - #ifdef CONFIG_E6500 mfspr r0,SPRN_PIR /* @@ -209,6 +202,13 @@ __secondary_start_page: mtspr SPRN_PIR,r4 /* write to PIR register */ +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* |