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author | Wills Wang <wills.wang@live.com> | 2016-05-30 22:54:54 +0800 |
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committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 10:17:54 +0200 |
commit | ca09e66b04cd2b80f95d5acc1cc7f61487034faf (patch) | |
tree | 716a5b29c4dcf7d337fb2f3845bbdfe7a97ba90a /arch/mips/mach-ath79/reset.c | |
parent | cdeb68e292358f9dedeaea167f6eba894c58823e (diff) | |
download | u-boot-ca09e66b04cd2b80f95d5acc1cc7f61487034faf.zip u-boot-ca09e66b04cd2b80f95d5acc1cc7f61487034faf.tar.gz u-boot-ca09e66b04cd2b80f95d5acc1cc7f61487034faf.tar.bz2 |
mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.
Signed-off-by: Wills Wang <wills.wang@live.com>
Diffstat (limited to 'arch/mips/mach-ath79/reset.c')
-rw-r--r-- | arch/mips/mach-ath79/reset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index a5ee141..073a179 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -89,7 +89,7 @@ static int eth_init_ar933x(void) mdelay(10); /* Get Atheros S26 PHY out of reset. */ - clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG, + clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG, 0x1f, 0x10); mdelay(10); |