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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:53 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | b2b135d980a7171c9b0eefbb38861ccbe9a47f97 (patch) | |
| tree | 21ec78ca322ced104ccc3066ba9b932b03a89015 /arch/mips/cpu/start.S | |
| parent | 5c72e5a62e998ce374a27b0589328bb284a27c8c (diff) | |
| download | u-boot-b2b135d980a7171c9b0eefbb38861ccbe9a47f97.zip u-boot-b2b135d980a7171c9b0eefbb38861ccbe9a47f97.tar.gz u-boot-b2b135d980a7171c9b0eefbb38861ccbe9a47f97.tar.bz2 | |
MIPS: Map CM Global Control Registers
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/cpu/start.S')
| -rw-r--r-- | arch/mips/cpu/start.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6f1d219..c157d03 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -141,6 +141,12 @@ reset: 1: PTR_L gp, 0(ra) +#ifdef CONFIG_MIPS_CM + PTR_LA t9, mips_cm_map + jalr t9 + nop +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ |