diff options
| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2023-07-10 14:37:37 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-07-21 09:00:39 +0200 |
| commit | a8d4b6700069f6717c65ee8ced63e525836ba855 (patch) | |
| tree | 76f360630352040600d011fdda3d31e5a7d2c651 /arch/arm | |
| parent | 1ea11e8138767a262e576d5b08bb1509fed62dd9 (diff) | |
| download | u-boot-a8d4b6700069f6717c65ee8ced63e525836ba855.zip u-boot-a8d4b6700069f6717c65ee8ced63e525836ba855.tar.gz u-boot-a8d4b6700069f6717c65ee8ced63e525836ba855.tar.bz2 | |
arm64: zynqmp: Add L2 cache nodes
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 38114d5..59b5291 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -33,6 +33,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { |