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authorVaralaxmi Bingi <varalaxmi.bingi@amd.com>2023-07-10 14:37:27 +0200
committerMichal Simek <michal.simek@amd.com>2023-07-21 09:00:38 +0200
commit39bdb9649810a1d664e21e92ae8b9553e798a0e8 (patch)
treeca8482c31b064dd81a563ebadf47e2dbf7e1fc6d /arch/arm
parented4a0ccb6e7d7fa2e8b92f5c07590a361a6efd30 (diff)
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arm: xilinx: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/dts/zynq-7000.dtsi2
-rw-r--r--arch/arm/dts/zynqmp.dtsi2
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 97a9e49..8c6eafe 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -153,6 +153,7 @@
clocks = <&clkc 38>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
+ clock-frequency = <400000>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -164,6 +165,7 @@
clocks = <&clkc 39>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
+ clock-frequency = <400000>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c9640c4..5f1e163 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -611,6 +611,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -622,6 +623,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;