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authorLey Foon Tan <ley.foon.tan@intel.com>2018-05-24 00:17:29 +0800
committerMarek Vasut <marex@denx.de>2018-07-12 09:22:12 +0200
commit73aede596cea7adc8e76dfbf92662cfc2eb0de5c (patch)
tree196c00f52e775eea5b0a03d1862268f80b85a17b /arch/arm
parent4765ddb0dab0ebd972f30725ca4397a93ee7272b (diff)
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arm: socfpga: stratix10: Add timer support for Stratix10 SoC
Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-socfpga/Makefile4
-rw-r--r--arch/arm/mach-socfpga/timer_s10.c26
2 files changed, 29 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 3131949..654999c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@ obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
-obj-y += timer.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
@@ -17,6 +16,7 @@ obj-y += misc_gen5.o
obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
+obj-y += timer.o
obj-y += wrap_pll_config.o
obj-y += fpga_manager.o
endif
@@ -26,6 +26,7 @@ obj-y += clock_manager_arria10.o
obj-y += misc_arria10.o
obj-y += pinmux_arria10.o
obj-y += reset_manager_arria10.o
+obj-y += timer.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
@@ -35,6 +36,7 @@ obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
+obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
new file mode 100644
index 0000000..5723789
--- /dev/null
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+ int enable = 0x3; /* timer enable + output signal masked */
+ int loadval = ~0;
+
+ /* enable system counter */
+ writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+ /* enable processor pysical counter */
+ asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+ asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+ return 0;
+}