db820c: add qualcomm dragonboard 820C support

This commit adds support for 96Boards Dragonboard820C.

The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.

Features
 - 4x Kyro CPU (64 bit) up to 2.15GHz
 - USB2.0
 - USB3.0
 - ISP
 - Qualcomm Hexagon DSP
 - SD 3.0 (UHS-I)
 - UFS 2.0
 - Qualcomm Adreno 530 GPU
 - GPS
 - BT 4.2
 - Wi-Fi 2.4GHz, 5GHz (802.11ac)
 - PCIe 2.0
 - MIPI-CSI, MIPI-DSI
 - I2S

U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.

For detailed build instructions see readme.txt in the board directory.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

7 files changed, 202 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bbc4f47..ee78cdd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -211,7 +211,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1012a-rdb.dtb \
 	fsl-ls1012a-frdm.dtb
 
-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
 
 dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
 	stm32f469-disco.dtb
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
new file mode 100644
index 0000000..2d49830
--- /dev/null
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -0,0 +1,65 @@
+/*
+ * Qualcomm APQ8096 based Dragonboard 820C board device tree source
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. DB820c";
+	compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &blsp2_uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@300000 {
+			compatible = "qcom,gcc-msm8996";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x300000 0x90000>;
+		};
+
+		blsp2_uart1: serial@75b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x75b0000 0x1000>;
+		};
+
+		sdhc2: sdhci@74a4900 {
+			 compatible = "qcom,sdhci-msm-v4";
+			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+			 index = <0x0>;
+			 bus-width = <4>;
+			 clock = <&gcc 0>;
+			clock-frequency = <200000000>;
+		 };
+	};
+};
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index dc7ba21..d55dc1a 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -19,8 +19,18 @@ config TARGET_DRAGONBOARD410C
 	  - HDMI
 	  - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
 
+config TARGET_DRAGONBOARD820C
+	bool "96Boards Dragonboard 820C"
+	help
+	  Support for 96Boards Dragonboard 820C. This board complies with
+	  96Board Open Platform Specifications. Features:
+	  - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
+	  - 3GiB RAM
+	  - 32GiB UFS drive
+
 endchoice
 
 source "board/qualcomm/dragonboard410c/Kconfig"
+source "board/qualcomm/dragonboard820c/Kconfig"
 
 endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index d798b82..090c355 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
 obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c
new file mode 100644
index 0000000..3d363d4
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -0,0 +1,62 @@
+/*
+ * Clock drivers for Qualcomm APQ8096
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS_ACTIVE		BIT(30)
+#define APCS_GPLL_ENA_VOTE_GPLL0	BIT(0)
+
+static const struct bcr_regs sdc_regs = {
+	.cfg_rcgr = SDCC2_CFG_RCGR,
+	.cmd_rcgr = SDCC2_CMD_RCGR,
+	.M = SDCC2_M,
+	.N = SDCC2_N,
+	.D = SDCC2_D,
+};
+
+static const struct gpll0_ctrl gpll0_ctrl = {
+	.status = GPLL0_STATUS,
+	.status_bit = GPLL0_STATUS_ACTIVE,
+	.ena_vote = APCS_GPLL_ENA_VOTE,
+	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+};
+
+static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
+{
+	int div = 3;
+
+	clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
+	clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
+			     CFG_CLK_SRC_GPLL0);
+	clk_enable_gpll0(priv->base, &gpll0_ctrl);
+	clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
+
+	return rate;
+}
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case 0: /* SDC1 */
+		return clk_init_sdc(priv, rate);
+		break;
+	default:
+		return 0;
+	}
+}
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
new file mode 100644
index 0000000..fb89de2
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
@@ -0,0 +1,29 @@
+/*
+ * Qualcomm APQ8096 sysmap
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8096_H
+#define _MACH_SYSMAP_APQ8096_H
+
+#define TLMM_BASE_ADDR			(0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG		(TLMM_BASE_ADDR + 0x0012D000)
+
+/* Clocks: (from CLK_CTL_BASE)  */
+#define GPLL0_STATUS			(0x0000)
+#define APCS_GPLL_ENA_VOTE		(0x52000)
+
+#define SDCC2_BCR			(0x14000) /* block reset */
+#define SDCC2_APPS_CBCR			(0x14004) /* branch control */
+#define SDCC2_AHB_CBCR			(0x14008)
+#define SDCC2_CMD_RCGR			(0x14010)
+#define SDCC2_CFG_RCGR			(0x14014)
+#define SDCC2_M				(0x14018)
+#define SDCC2_N				(0x1401C)
+#define SDCC2_D				(0x14020)
+
+#endif
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c
new file mode 100644
index 0000000..cb6d1e4
--- /dev/null
+++ b/arch/arm/mach-snapdragon/sysmap-apq8096.c
@@ -0,0 +1,32 @@
+/*
+ * Qualcomm APQ8096 memory map
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region apq8096_mem_map[] = {
+	{
+		.virt = 0x0UL, /* Peripheral block */
+		.phys = 0x0UL, /* Peripheral block */
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL, /* DDR */
+		.phys = 0x80000000UL, /* DDR */
+		.size = 0xC0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = apq8096_mem_map;