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| author | Tom Rini <trini@konsulko.com> | 2020-10-29 11:30:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-10-29 11:30:15 -0400 |
| commit | 47754334b164eae4fde538c406ff3678dfb05042 (patch) | |
| tree | 5683d789f5b9b57d0006dbfbb0f7d03782deca10 /arch/arm/mach-zynqmp/include/mach/sys_proto.h | |
| parent | cdeb7b8f984e6d9bcdc5a6fdda6107af156d47bf (diff) | |
| parent | 908daf86f96a44176ecd1e04f1ec71e143aa45f5 (diff) | |
| download | u-boot-47754334b164eae4fde538c406ff3678dfb05042.zip u-boot-47754334b164eae4fde538c406ff3678dfb05042.tar.gz u-boot-47754334b164eae4fde538c406ff3678dfb05042.tar.bz2 | |
Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Diffstat (limited to 'arch/arm/mach-zynqmp/include/mach/sys_proto.h')
| -rw-r--r-- | arch/arm/mach-zynqmp/include/mach/sys_proto.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index f2b3cea..1c12eac 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -9,6 +9,16 @@ #define ZYNQMP_CSU_SILICON_VER_MASK 0xF #define KEY_PTR_LEN 32 +#define IV_SIZE 12 +#define RSA_KEY_SIZE 512 +#define MODULUS_LEN 512 +#define PRIV_EXPO_LEN 512 +#define PUB_EXPO_LEN 4 + +#define ZYNQMP_SHA3_INIT 1 +#define ZYNQMP_SHA3_UPDATE 2 +#define ZYNQMP_SHA3_FINAL 4 +#define ZYNQMP_SHA3_SIZE 48 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 |