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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-08-26 17:57:59 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-08-30 09:03:11 +0900 |
| commit | a55957b9ad0b912b9e0f705ed64e42274be05276 (patch) | |
| tree | ba2a62bd8d135ec1003294365ccea1624aba875f /arch/arm/mach-uniphier/sc64-regs.h | |
| parent | 546197b98629fa66a125f87a2b7b61cb8bec6c39 (diff) | |
| download | u-boot-a55957b9ad0b912b9e0f705ed64e42274be05276.zip u-boot-a55957b9ad0b912b9e0f705ed64e42274be05276.tar.gz u-boot-a55957b9ad0b912b9e0f705ed64e42274be05276.tar.bz2 | |
ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name. We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file. Also, fix some PLL comments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/sc64-regs.h')
| -rw-r--r-- | arch/arm/mach-uniphier/sc64-regs.h | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d3aa185..d0a51f2 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -12,27 +12,6 @@ #define SC_BASE_ADDR 0x61840000 -/* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ - -/* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) - -/* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) - #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) |