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| author | Stephen Warren <swarren@nvidia.com> | 2018-01-04 11:07:14 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2018-01-12 10:12:32 -0700 |
| commit | cdcf55584e7e6b9be92a258d70d4d08a0216dbd0 (patch) | |
| tree | d1b1418a93814660f168e2fbcfacf7a91859634c /arch/arm/mach-tegra/arm64-mmu.c | |
| parent | a9819b9e33bd9e8e2bdb694abef78397d8c00e7f (diff) | |
| download | u-boot-cdcf55584e7e6b9be92a258d70d4d08a0216dbd0.zip u-boot-cdcf55584e7e6b9be92a258d70d4d08a0216dbd0.tar.gz u-boot-cdcf55584e7e6b9be92a258d70d4d08a0216dbd0.tar.bz2 | |
ARM: Tegra186: don't map memory not in RAM banks
Tegra186 currently restricts its DRAM usage to entries in the /memory node
in the DTB passed to it. However, the MMU configuration always maps the
entire first 2GB of RAM. This could allow the CPU to speculatively access
RAM that isn't part of the in-use banks. This patch switches to runtime
construction of the table that's used to construct the MMU translation
tables, and thus prevents access to RAM that's not part of a valid bank.
Note: This patch is intended to prevent access to RAM regions which U-Boot
does not need to access, with the primary purpose of avoiding theoretical
speculative access to physical regions for which the HW will throw errors
(e.g. carve-outs that the CPU has no permission to access at a bus level,
bad ECC pages, etc.). In particular, this patch is not deliberately
related to the speculation-related security issues that were recently
announced. The apparent similarity is a coincidence.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/arm64-mmu.c')
| -rw-r--r-- | arch/arm/mach-tegra/arm64-mmu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index a79a519..3a126bd 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -12,7 +12,8 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> -static struct mm_region tegra_mem_map[] = { +/* size: IO + NR_DRAM_BANKS + terminator */ +struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { { .virt = 0x0UL, .phys = 0x0UL, |