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authorAndre Przywara <andre.przywara@arm.com>2020-01-28 00:46:42 +0000
committerJagan Teki <jagan@amarulasolutions.com>2020-03-18 18:11:53 +0530
commitda19a0dbc817fcda7a564360767e02b5c174cf1e (patch)
tree6e1e94e6f947444da5d7afe90688dd33e1ef1c53 /arch/arm/mach-sunxi
parent56f51f3875144822415757f1887d2254b6b8e937 (diff)
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sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC
Now that we can easily select an SoC specific SPI0 base address, adding support for the Allwinner R40 is fairly trivial: We set the base address, add this SoC to the ones that use PC23 and enable it in Kconfig. This allows booting from SPI flash on R40 boards. Tested on a Bananapi M2 Berry with SPI flash connected to the header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
-rw-r--r--arch/arm/mach-sunxi/Kconfig2
-rw-r--r--arch/arm/mach-sunxi/spl_spi_sunxi.c6
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3a3b673..eb04616 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index cab6aff..357953c 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -94,7 +94,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
+ IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
@@ -107,6 +108,9 @@ static bool is_sun6i_gen_spi(void)
static uintptr_t spi0_base_address(void)
{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
+ return 0x01C05000;
+
if (!is_sun6i_gen_spi())
return 0x01C05000;