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| author | Wolfgang Denk <wd@denx.de> | 2021-09-27 17:42:39 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-30 09:08:16 -0400 |
| commit | 0cf207ec01cbacae47585fcc26591dd2296507d6 (patch) | |
| tree | 573cfefc2ab21a033ae98fa2afbd57f1f6528496 /arch/arm/mach-sunxi | |
| parent | 0a50b3c97b3408e52589d873d4c7b54ad365a76c (diff) | |
| download | u-boot-0cf207ec01cbacae47585fcc26591dd2296507d6.zip u-boot-0cf207ec01cbacae47585fcc26591dd2296507d6.tar.gz u-boot-0cf207ec01cbacae47585fcc26591dd2296507d6.tar.bz2 | |
WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun4i.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun8i_a33.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c index 76d6982..80a6c4b 100644 --- a/arch/arm/mach-sunxi/dram_sun4i.c +++ b/arch/arm/mach-sunxi/dram_sun4i.c @@ -279,7 +279,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); - } else { + } else { /* any other frequency that is a multiple of 24 */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index d99a38b..367b740 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -126,8 +126,8 @@ static void auto_set_timing_para(struct dram_para *para) u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ /* Set work mode register */ mctl_set_cr(para); diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index 611eaa3..2136ca3 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -30,7 +30,7 @@ * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2, * write levelling disabled, TDQS disabled, output buffer enabled * MR2: manual full array self refresh, dynamic ODT off, - * CAS write latency (CWL): 8 + * CAS write latency (CWL): 8 */ static u32 mr_ddr3[7] = { 0x00001c70, 0x00000040, 0x00000018, 0x00000000, |