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authorTom Rini <trini@konsulko.com>2018-04-18 13:50:47 -0400
committerTom Rini <trini@konsulko.com>2018-04-27 14:54:48 -0400
commitd024236e5a31a2b4b82cbcc98b31b8170fc88d28 (patch)
treeab4d96f1b0c5e3991b97708f72679a7af7234222 /arch/arm/mach-socfpga
parentf1b1f77060beadbfe9f42a3be00019bd025afbd6 (diff)
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Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/clock_manager_arria10.c2
-rw-r--r--arch/arm/mach-socfpga/clock_manager_gen5.c2
-rw-r--r--arch/arm/mach-socfpga/fpga_manager.c2
-rw-r--r--arch/arm/mach-socfpga/freeze_controller.c2
-rw-r--r--arch/arm/mach-socfpga/misc_arria10.c2
-rw-r--r--arch/arm/mach-socfpga/reset_manager.c2
-rw-r--r--arch/arm/mach-socfpga/reset_manager_gen5.c2
-rw-r--r--arch/arm/mach-socfpga/scan_manager.c2
-rw-r--r--arch/arm/mach-socfpga/system_manager_gen5.c2
9 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 623a266..4bc4acb 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -10,8 +10,6 @@
#include <dm.h>
#include <asm/arch/clock_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 4e5b6d1..1b3914b 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -10,8 +10,6 @@
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
index f909573..16e4a78 100644
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ b/arch/arm/mach-socfpga/fpga_manager.c
@@ -15,8 +15,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c
index 71d5d99..62fa854 100644
--- a/arch/arm/mach-socfpga/freeze_controller.c
+++ b/arch/arm/mach-socfpga/freeze_controller.c
@@ -11,8 +11,6 @@
#include <asm/arch/freeze_controller.h>
#include <linux/errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 9d751f6..475fd59 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -28,8 +28,6 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 29438ed..484b295 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -9,8 +9,6 @@
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index aa88adb..c591274 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -11,8 +11,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index 566b33f..8b271b1 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -28,8 +28,6 @@
#define SCANMGR_STAT_ACTIVE (1 << 31)
#define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =
diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
index 3588a57..e0af775 100644
--- a/arch/arm/mach-socfpga/system_manager_gen5.c
+++ b/arch/arm/mach-socfpga/system_manager_gen5.c
@@ -9,8 +9,6 @@
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;