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author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 10:38:19 +0800 |
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committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
commit | bb25aca1343304e0334e9eebfb9d350eaf276882 (patch) | |
tree | 00e8e1c3b79e4a6175bfeccf716d106ec02593cc /arch/arm/mach-socfpga/spl_gen5.c | |
parent | dd72cbd9e91dfa80f04a5921546d19e189bb2361 (diff) | |
download | u-boot-bb25aca1343304e0334e9eebfb9d350eaf276882.zip u-boot-bb25aca1343304e0334e9eebfb9d350eaf276882.tar.gz u-boot-bb25aca1343304e0334e9eebfb9d350eaf276882.tar.bz2 |
arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/spl_gen5.c')
-rw-r--r-- | arch/arm/mach-socfpga/spl_gen5.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 408e409..bbaa5d3 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -67,8 +67,14 @@ void board_init_f(ulong dummy) int ret; struct udevice *dev; + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + /* - * First C code to run. Clear fake OCRAM ECC first as SBE + * Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); @@ -128,12 +134,6 @@ void board_init_f(ulong dummy) debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - ret = uclass_get_device(UCLASS_RESET, 0, &dev); if (ret) debug("Reset init failed: %d\n", ret); |