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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:18 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | 2fd1dc5593d6ea0266797009dd702279fd10f7d1 (patch) | |
| tree | 628a901f5731bc663b0231a11c818b0c641b4e5c /arch/arm/mach-socfpga/reset_manager_s10.c | |
| parent | 50278d4adea6f91e266c84e5df7ee3efa5aeb573 (diff) | |
| download | u-boot-2fd1dc5593d6ea0266797009dd702279fd10f7d1.zip u-boot-2fd1dc5593d6ea0266797009dd702279fd10f7d1.tar.gz u-boot-2fd1dc5593d6ea0266797009dd702279fd10f7d1.tar.bz2 | |
arm: socfpga: Move Stratix10 and Agilex system manager common code
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager_s10.c')
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f449cb6..c743077 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -57,7 +57,7 @@ void socfpga_bridges_reset(int enable) if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_S10_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); /* Release all bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, @@ -65,23 +65,24 @@ void socfpga_bridges_reset(int enable) /* Poll until all idleack to 0 */ while (readl(socfpga_get_sysmgr_addr() + - SYSMGR_S10_NOC_IDLEACK)) + SYSMGR_SOC64_NOC_IDLEACK)) ; } else { /* set idle request to all bridges */ writel(~0, - socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEREQ_SET); + socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET); /* Enable the NOC timeout */ - writel(1, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT); + writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEACK) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; /* Poll until all idlestatus to 1 */ - while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLESTATUS) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; @@ -91,7 +92,7 @@ void socfpga_bridges_reset(int enable) RSTMGR_BRGMODRST_FPGA2SOC_MASK)); /* Disable NOC timeout */ - writel(0, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } } |