arm: socfpga: Convert clock manager from struct to defines

Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

4 files changed, 147 insertions, 215 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index dd80e3a..6de7cae 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -6,6 +6,8 @@
 #ifndef _CLOCK_MANAGER_H_
 #define _CLOCK_MANAGER_H_
 
+phys_addr_t socfpga_get_clkmgr_addr(void);
+
 #ifndef __ASSEMBLER__
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index de8c225..23f280d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -8,86 +8,57 @@
 
 #ifndef __ASSEMBLER__
 
-struct socfpga_clock_manager_main_pll {
-	u32  vco0;
-	u32  vco1;
-	u32  en;
-	u32  ens;
-	u32  enr;
-	u32  bypass;
-	u32  bypasss;
-	u32  bypassr;
-	u32  mpuclk;
-	u32  nocclk;
-	u32  cntr2clk;
-	u32  cntr3clk;
-	u32  cntr4clk;
-	u32  cntr5clk;
-	u32  cntr6clk;
-	u32  cntr7clk;
-	u32  cntr8clk;
-	u32  cntr9clk;
-	u32  pad_0x48_0x5b[5];
-	u32  cntr15clk;
-	u32  outrst;
-	u32  outrststat;
-	u32  nocdiv;
-	u32  pad_0x6c_0x80[5];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32  vco0;
-	u32  vco1;
-	u32  en;
-	u32  ens;
-	u32  enr;
-	u32  bypass;
-	u32  bypasss;
-	u32  bypassr;
-	u32  pad_0x20_0x27[2];
-	u32  cntr2clk;
-	u32  cntr3clk;
-	u32  cntr4clk;
-	u32  cntr5clk;
-	u32  cntr6clk;
-	u32  cntr7clk;
-	u32  cntr8clk;
-	u32  cntr9clk;
-	u32  pad_0x48_0x5f[6];
-	u32  outrst;
-	u32  outrststat;
-	u32  emacctl;
-	u32  gpiodiv;
-	u32  pad_0x70_0x80[4];
-};
-
-struct socfpga_clock_manager_altera {
-	u32	mpuclk;
-	u32	nocclk;
-	u32	mainmisc0;
-	u32	mainmisc1;
-	u32	perimisc0;
-	u32	perimisc1;
-};
-
-struct socfpga_clock_manager {
-	/* clkmgr */
-	u32  ctrl;
-	u32  intr;
-	u32  intrs;
-	u32  intrr;
-	u32  intren;
-	u32  intrens;
-	u32  intrenr;
-	u32  stat;
-	u32  testioctrl;
-	u32  _pad_0x24_0x40[7];
-	/* mainpllgrp */
-	struct socfpga_clock_manager_main_pll main_pll;
-	/* perpllgrp */
-	struct socfpga_clock_manager_per_pll per_pll;
-	struct socfpga_clock_manager_altera altera;
-};
+/* Clock manager group */
+#define CLKMGR_A10_CTRL				0x00
+#define CLKMGR_A10_INTR				0x04
+#define CLKMGR_A10_STAT				0x1c
+/* MainPLL group */
+#define CLKMGR_A10_MAINPLL_VCO0			0x40
+#define CLKMGR_A10_MAINPLL_VCO1			0x44
+#define CLKMGR_A10_MAINPLL_EN			0x48
+#define CLKMGR_A10_MAINPLL_ENS			0x4c
+#define CLKMGR_A10_MAINPLL_ENR			0x50
+#define CLKMGR_A10_MAINPLL_BYPASS		0x54
+#define CLKMGR_A10_MAINPLL_BYPASSS		0x58
+#define CLKMGR_A10_MAINPLL_BYPASSR		0x5c
+#define CLKMGR_A10_MAINPLL_MPUCLK		0x60
+#define CLKMGR_A10_MAINPLL_NOCCLK		0x64
+#define CLKMGR_A10_MAINPLL_CNTR2CLK		0x68
+#define CLKMGR_A10_MAINPLL_CNTR3CLK		0x6c
+#define CLKMGR_A10_MAINPLL_CNTR4CLK		0x70
+#define CLKMGR_A10_MAINPLL_CNTR5CLK		0x74
+#define CLKMGR_A10_MAINPLL_CNTR6CLK		0x78
+#define CLKMGR_A10_MAINPLL_CNTR7CLK		0x7c
+#define CLKMGR_A10_MAINPLL_CNTR8CLK		0x80
+#define CLKMGR_A10_MAINPLL_CNTR9CLK		0x84
+#define CLKMGR_A10_MAINPLL_CNTR15CLK		0x9c
+#define CLKMGR_A10_MAINPLL_NOCDIV		0xa8
+/* Peripheral PLL group */
+#define CLKMGR_A10_PERPLL_VCO0			0xc0
+#define CLKMGR_A10_PERPLL_VCO1			0xc4
+#define CLKMGR_A10_PERPLL_EN			0xc8
+#define CLKMGR_A10_PERPLL_ENS			0xcc
+#define CLKMGR_A10_PERPLL_ENR			0xd0
+#define CLKMGR_A10_PERPLL_BYPASS		0xd4
+#define CLKMGR_A10_PERPLL_BYPASSS		0xd8
+#define CLKMGR_A10_PERPLL_BYPASSR		0xdc
+#define CLKMGR_A10_PERPLL_CNTR2CLK		0xe8
+#define CLKMGR_A10_PERPLL_CNTR3CLK		0xec
+#define CLKMGR_A10_PERPLL_CNTR4CLK		0xf0
+#define CLKMGR_A10_PERPLL_CNTR5CLK		0xf4
+#define CLKMGR_A10_PERPLL_CNTR6CLK		0xf8
+#define CLKMGR_A10_PERPLL_CNTR7CLK		0xfc
+#define CLKMGR_A10_PERPLL_CNTR8CLK		0x100
+#define CLKMGR_A10_PERPLL_CNTR9CLK		0x104
+#define CLKMGR_A10_PERPLL_EMACCTL		0x128
+#define CLKMGR_A10_PERPLL_GPIOFIV		0x12c
+/* Altera group */
+#define CLKMGR_A10_ALTR_MPUCLK			0x140
+#define CLKMGR_A10_ALTR_NOCCLK			0x144
+
+#define CLKMGR_STAT				CLKMGR_A10_STAT
+#define CLKMGR_INTER				CLKMGR_A10_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_A10_PERPLL_EN
 
 #ifdef CONFIG_SPL_BUILD
 int cm_basic_init(const void *blob);
@@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 #endif /* __ASSEMBLER__ */
 
-#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET			0x140
-#define CLKMGR_MAINPLL_NOC_CLK_OFFSET			0x144
 #define LOCKED_MASK	(CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
 			 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
 
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 5bedf28..0865509 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -45,71 +45,53 @@ struct cm_config {
 	u32 altera_grp_mpuclk;
 };
 
-struct socfpga_clock_manager_main_pll {
-	u32	vco;
-	u32	misc;
-	u32	mpuclk;
-	u32	mainclk;
-	u32	dbgatclk;
-	u32	mainqspiclk;
-	u32	mainnandsdmmcclk;
-	u32	cfgs2fuser0clk;
-	u32	en;
-	u32	maindiv;
-	u32	dbgdiv;
-	u32	tracediv;
-	u32	l4src;
-	u32	stat;
-	u32	_pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32	vco;
-	u32	misc;
-	u32	emac0clk;
-	u32	emac1clk;
-	u32	perqspiclk;
-	u32	pernandsdmmcclk;
-	u32	perbaseclk;
-	u32	s2fuser1clk;
-	u32	en;
-	u32	div;
-	u32	gpiodiv;
-	u32	src;
-	u32	stat;
-	u32	_pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
-	u32	vco;
-	u32	ctrl;
-	u32	ddrdqsclk;
-	u32	ddr2xdqsclk;
-	u32	ddrdqclk;
-	u32	s2fuser2clk;
-	u32	en;
-	u32	stat;
-};
-
-struct socfpga_clock_manager_altera {
-	u32	mpuclk;
-	u32	mainclk;
-};
-
-struct socfpga_clock_manager {
-	u32	ctrl;
-	u32	bypass;
-	u32	inter;
-	u32	intren;
-	u32	dbctrl;
-	u32	stat;
-	u32	_pad_0x18_0x3f[10];
-	struct socfpga_clock_manager_main_pll main_pll;
-	struct socfpga_clock_manager_per_pll per_pll;
-	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	struct socfpga_clock_manager_altera altera;
-	u32	_pad_0xe8_0x200[70];
-};
+/* Clock manager group */
+#define CLKMGR_GEN5_CTRL			0x00
+#define CLKMGR_GEN5_BYPASS			0x04
+#define CLKMGR_GEN5_INTER			0x08
+#define CLKMGR_GEN5_STAT			0x14
+/* MainPLL group */
+#define CLKMGR_GEN5_MAINPLL_VCO			0x40
+#define CLKMGR_GEN5_MAINPLL_MISC		0x44
+#define CLKMGR_GEN5_MAINPLL_MPUCLK		0x48
+#define CLKMGR_GEN5_MAINPLL_MAINCLK		0x4c
+#define CLKMGR_GEN5_MAINPLL_DBGATCLK		0x50
+#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK		0x54
+#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK	0x58
+#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK	0x5c
+#define CLKMGR_GEN5_MAINPLL_EN			0x60
+#define CLKMGR_GEN5_MAINPLL_MAINDIV		0x64
+#define CLKMGR_GEN5_MAINPLL_DBGDIV		0x68
+#define CLKMGR_GEN5_MAINPLL_TRACEDIV		0x6c
+#define CLKMGR_GEN5_MAINPLL_L4SRC		0x70
+/* Peripheral PLL group */
+#define CLKMGR_GEN5_PERPLL_VCO			0x80
+#define CLKMGR_GEN5_PERPLL_MISC			0x84
+#define CLKMGR_GEN5_PERPLL_EMAC0CLK		0x88
+#define CLKMGR_GEN5_PERPLL_EMAC1CLK		0x8c
+#define CLKMGR_GEN5_PERPLL_PERQSPICLK		0x90
+#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK	0x94
+#define CLKMGR_GEN5_PERPLL_PERBASECLK		0x98
+#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK		0x9c
+#define CLKMGR_GEN5_PERPLL_EN			0xa0
+#define CLKMGR_GEN5_PERPLL_DIV			0xa4
+#define CLKMGR_GEN5_PERPLL_GPIODIV		0xa8
+#define CLKMGR_GEN5_PERPLL_SRC			0xac
+/* SDRAM PLL group */
+#define CLKMGR_GEN5_SDRPLL_VCO			0xc0
+#define CLKMGR_GEN5_SDRPLL_CTRL			0xc4
+#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK		0xc8
+#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK		0xcc
+#define CLKMGR_GEN5_SDRPLL_DDRDQCLK		0xd0
+#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK		0xd4
+#define CLKMGR_GEN5_SDRPLL_EN			0xd8
+/* Altera group */
+#define CLKMGR_GEN5_ALTR_MPUCLK			0xe0
+#define CLKMGR_GEN5_ALTR_MAINCLK		0xe4
+
+#define CLKMGR_STAT				CLKMGR_GEN5_STAT
+#define CLKMGR_INTER				CLKMGR_GEN5_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_GEN5_PERPLL_EN
 
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 24b20de..13eb235 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -69,75 +69,54 @@ struct cm_config {
 
 void cm_basic_init(const struct cm_config * const cfg);
 
-struct socfpga_clock_manager_main_pll {
-	u32	en;
-	u32	ens;
-	u32	enr;
-	u32	bypass;
-	u32	bypasss;
-	u32	bypassr;
-	u32	mpuclk;
-	u32	nocclk;
-	u32	cntr2clk;
-	u32	cntr3clk;
-	u32	cntr4clk;
-	u32	cntr5clk;
-	u32	cntr6clk;
-	u32	cntr7clk;
-	u32	cntr8clk;
-	u32	cntr9clk;
-	u32	nocdiv;
-	u32	pllglob;
-	u32	fdbck;
-	u32	mem;
-	u32	memstat;
-	u32	pllc0;
-	u32	pllc1;
-	u32	vcocalib;
-	u32	_pad_0x90_0xA0[5];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32	en;
-	u32	ens;
-	u32	enr;
-	u32	bypass;
-	u32	bypasss;
-	u32	bypassr;
-	u32	cntr2clk;
-	u32	cntr3clk;
-	u32	cntr4clk;
-	u32	cntr5clk;
-	u32	cntr6clk;
-	u32	cntr7clk;
-	u32	cntr8clk;
-	u32	cntr9clk;
-	u32	emacctl;
-	u32	gpiodiv;
-	u32	pllglob;
-	u32	fdbck;
-	u32	mem;
-	u32	memstat;
-	u32	pllc0;
-	u32	pllc1;
-	u32	vcocalib;
-	u32	_pad_0x100_0x124[10];
-};
+/* Control status */
+#define CLKMGR_S10_CTRL					0x00
+#define CLKMGR_S10_STAT					0x04
+#define CLKMGR_S10_INTRCLR				0x14
+/* Mainpll group */
+#define CLKMGR_S10_MAINPLL_EN				0x30
+#define CLKMGR_S10_MAINPLL_BYPASS			0x3c
+#define CLKMGR_S10_MAINPLL_MPUCLK			0x48
+#define CLKMGR_S10_MAINPLL_NOCCLK			0x4c
+#define CLKMGR_S10_MAINPLL_CNTR2CLK			0x50
+#define CLKMGR_S10_MAINPLL_CNTR3CLK			0x54
+#define CLKMGR_S10_MAINPLL_CNTR4CLK			0x58
+#define CLKMGR_S10_MAINPLL_CNTR5CLK			0x5c
+#define CLKMGR_S10_MAINPLL_CNTR6CLK			0x60
+#define CLKMGR_S10_MAINPLL_CNTR7CLK			0x64
+#define CLKMGR_S10_MAINPLL_CNTR8CLK			0x68
+#define CLKMGR_S10_MAINPLL_CNTR9CLK			0x6c
+#define CLKMGR_S10_MAINPLL_NOCDIV			0x70
+#define CLKMGR_S10_MAINPLL_PLLGLOB			0x74
+#define CLKMGR_S10_MAINPLL_FDBCK			0x78
+#define CLKMGR_S10_MAINPLL_MEMSTAT			0x80
+#define CLKMGR_S10_MAINPLL_PLLC0			0x84
+#define CLKMGR_S10_MAINPLL_PLLC1			0x88
+#define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
+/* Periphpll group */
+#define CLKMGR_S10_PERPLL_EN				0xa4
+#define CLKMGR_S10_PERPLL_BYPASS			0xac
+#define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
+#define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
+#define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4
+#define CLKMGR_S10_PERPLL_CNTR5CLK			0xc8
+#define CLKMGR_S10_PERPLL_CNTR6CLK			0xcc
+#define CLKMGR_S10_PERPLL_CNTR7CLK			0xd0
+#define CLKMGR_S10_PERPLL_CNTR8CLK			0xd4
+#define CLKMGR_S10_PERPLL_CNTR9CLK			0xd8
+#define CLKMGR_S10_PERPLL_EMACCTL			0xdc
+#define CLKMGR_S10_PERPLL_GPIODIV			0xe0
+#define CLKMGR_S10_PERPLL_PLLGLOB			0xe4
+#define CLKMGR_S10_PERPLL_FDBCK				0xe8
+#define CLKMGR_S10_PERPLL_MEMSTAT			0xf0
+#define CLKMGR_S10_PERPLL_PLLC0				0xf4
+#define CLKMGR_S10_PERPLL_PLLC1				0xf8
+#define CLKMGR_S10_PERPLL_VCOCALIB			0xfc
+
+#define CLKMGR_STAT					CLKMGR_S10_STAT
+#define CLKMGR_INTER					CLKMGR_S10_INTER
+#define CLKMGR_PERPLL_EN				CLKMGR_S10_PERPLL_EN
 
-struct socfpga_clock_manager {
-	u32	ctrl;
-	u32	stat;
-	u32	testioctrl;
-	u32	intrgen;
-	u32	intrmsk;
-	u32	intrclr;
-	u32	intrsts;
-	u32	intrstk;
-	u32	intrraw;
-	u32	_pad_0x24_0x2c[3];
-	struct socfpga_clock_manager_main_pll main_pll;
-	struct socfpga_clock_manager_per_pll per_pll;
-};
 
 #define CLKMGR_CTRL_SAFEMODE				BIT(0)
 #define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007