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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2019-05-07 17:42:30 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-10 22:48:11 +0200 |
| commit | 1085bb3cbaf8321fdc8d0eaa367192433bd51d44 (patch) | |
| tree | 099e967755262df7e02f0ce5a23172cfb2373f93 /arch/arm/mach-socfpga/include | |
| parent | f61d52926086bf56c870f06ba5e88bdb41ac246e (diff) | |
| download | u-boot-1085bb3cbaf8321fdc8d0eaa367192433bd51d44.zip u-boot-1085bb3cbaf8321fdc8d0eaa367192433bd51d44.tar.gz u-boot-1085bb3cbaf8321fdc8d0eaa367192433bd51d44.tar.bz2 | |
spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index c5f6771..62249b3 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -126,6 +126,7 @@ int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); const char *get_fpga_filename(void); +int is_fpgamgr_early_user_mode(void); int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, u32 offset); void fpgamgr_program(const void *buf, size_t bsize, u32 offset); |