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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2017-04-26 02:44:36 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-05-18 11:33:17 +0200 |
| commit | d1c559af5fb1a513eef1adf37713659d4e4e1968 (patch) | |
| tree | 03800cbace202cc91be5802fadbb4f16b9bb71d9 /arch/arm/mach-socfpga/Makefile | |
| parent | 4ddd541d6ceabcf4aeb553373f9ab501a44ed90d (diff) | |
| download | u-boot-d1c559af5fb1a513eef1adf37713659d4e4e1968.zip u-boot-d1c559af5fb1a513eef1adf37713659d4e4e1968.tar.gz u-boot-d1c559af5fb1a513eef1adf37713659d4e4e1968.tar.bz2 | |
arm: socfpga: Restructure misc driver
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Makefile')
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 4980e51..e83da2e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ clock_manager_gen5.o reset_manager_gen5.o \ - system_manager_gen5.o + misc_gen5.o system_manager_gen5.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) |