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| author | Siew Chin Lim <elly.siew.chin.lim@intel.com> | 2021-08-10 11:26:42 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-08-25 15:26:38 +0800 |
| commit | 31b51cb1d2b4114085cb5565502d39d6f6daa2a7 (patch) | |
| tree | e4e4493f312df8049af201a0376193de60a50c01 /arch/arm/mach-socfpga/Kconfig | |
| parent | ed9050f87eebef6478e20e9156fa4c6db6fbb688 (diff) | |
| download | u-boot-31b51cb1d2b4114085cb5565502d39d6f6daa2a7.zip u-boot-31b51cb1d2b4114085cb5565502d39d6f6daa2a7.tar.gz u-boot-31b51cb1d2b4114085cb5565502d39d6f6daa2a7.tar.bz2 | |
arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Kconfig')
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 0c35406..f4791c1 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -8,7 +8,7 @@ config NR_DRAM_BANKS config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX + depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512_ALGO @@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF +config TARGET_SOCFPGA_N5X + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select NCORE_CACHE + select SPL_ALTERA_SDRAM + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + +config TARGET_SOCFPGA_N5X_SOCDK + bool "Intel eASIC SoCDK (N5X)" + select TARGET_SOCFPGA_N5X + config TARGET_SOCFPGA_SOC64 bool @@ -185,6 +201,7 @@ config SYS_BOARD default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK + default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES @@ -194,6 +211,7 @@ config SYS_BOARD config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK + default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -223,6 +241,7 @@ config SYS_CONFIG_NAME default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "socfpga_is1" if TARGET_SOCFPGA_IS1 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK + default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |