diff options
| author | Sumit Garg <sumit.garg@linaro.org> | 2022-08-04 19:57:14 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-26 10:55:45 -0400 |
| commit | c9e384e9b6f32070b2c4ac51b2315e5719765811 (patch) | |
| tree | 797e2d612e8f7e757325aec68eb1d68474939921 /arch/arm/mach-snapdragon | |
| parent | 21ed4563cb942bdbe928a5366e02a130db74f13b (diff) | |
| download | u-boot-c9e384e9b6f32070b2c4ac51b2315e5719765811.zip u-boot-c9e384e9b6f32070b2c4ac51b2315e5719765811.tar.gz u-boot-c9e384e9b6f32070b2c4ac51b2315e5719765811.tar.bz2 | |
clocks: qcom: Add clock enable callback support
Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks.
So add corresponding support for Qcom clock drivers.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Diffstat (limited to 'arch/arm/mach-snapdragon')
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-apq8016.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-apq8096.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-qcs404.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-sdm845.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-snapdragon.c | 7 |
5 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 6e4a0cc..23a37a1 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -111,3 +111,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index e5011be..6618459 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -93,3 +93,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index bb8a6fe..230d777 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -77,3 +77,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c index f69be80..d6df036 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -91,3 +91,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 5652d2f..fda7098 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -20,6 +20,7 @@ #define CBCR_BRANCH_OFF_BIT BIT(31) extern ulong msm_set_rate(struct clk *clk, ulong rate); +extern int msm_enable(struct clk *clk); /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) @@ -126,8 +127,14 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate) return msm_set_rate(clk, rate); } +static int msm_clk_enable(struct clk *clk) +{ + return msm_enable(clk); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, + .enable = msm_clk_enable, }; static const struct udevice_id msm_clk_ids[] = { |