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| author | Sumit Garg <sumit.garg@linaro.org> | 2022-07-12 12:42:10 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-07-25 13:02:04 -0400 |
| commit | a8effc2ee4db60a8e9ef722f612f0d484c137e49 (patch) | |
| tree | aa423d5ad20bb2cecbbb199af4a93b5253688c73 /arch/arm/mach-snapdragon | |
| parent | 364c22a84aa180ab8fe94f9983484c4da26e3bd6 (diff) | |
| download | u-boot-a8effc2ee4db60a8e9ef722f612f0d484c137e49.zip u-boot-a8effc2ee4db60a8e9ef722f612f0d484c137e49.tar.gz u-boot-a8effc2ee4db60a8e9ef722f612f0d484c137e49.tar.bz2 | |
pinctrl: qcom: Add pinctrl driver for QCS404 SoC
Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Diffstat (limited to 'arch/arm/mach-snapdragon')
| -rw-r--r-- | arch/arm/mach-snapdragon/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 |
4 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 962855e..cb8c1aa 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -15,4 +15,5 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-y += pinctrl-qcs404.o obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c new file mode 100644 index 0000000..889ead0 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QCS404 pinctrl + * + * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); +static const char * const msm_pinctrl_pins[] = { + "SDC1_RCLK", + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart2", 1}, +}; + +static const char *qcs404_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcs404_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 120) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 120]; + } +} + +static unsigned int qcs404_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcs404_data = { + .pin_count = 126, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcs404_get_function_name, + .get_function_mux = qcs404_get_function_mux, + .get_pin_name = qcs404_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index d1c560d..c2148a5 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { #ifdef CONFIG_SDM845 { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, #endif + { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index ea52431..178ee01 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -28,5 +28,6 @@ struct pinctrl_function { extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; extern struct msm_pinctrl_data sdm845_data; +extern struct msm_pinctrl_data qcs404_data; #endif |