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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-09-16 13:47:15 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-11 13:31:17 -0400 |
| commit | ed474ae00c7b2b51fc97b0580d2e52483a657acb (patch) | |
| tree | 1c7f0a0cde2cdb523a89b993b31f1e79a59c3b16 /arch/arm/mach-omap2 | |
| parent | 3d95fc523e818f786cf505403052399a3236623f (diff) | |
| download | u-boot-ed474ae00c7b2b51fc97b0580d2e52483a657acb.zip u-boot-ed474ae00c7b2b51fc97b0580d2e52483a657acb.tar.gz u-boot-ed474ae00c7b2b51fc97b0580d2e52483a657acb.tar.bz2 | |
arm: omap: emif-common: Fix ecc address calculation
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/emif-common.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index b384343..04bbfd8 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -348,7 +348,7 @@ static void dra7_reset_ddr_data(u32 base, u32 size) static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 rgn, size; + u32 rgn, rgn_start, size; /* ECC available only on dra76x EMIF1 */ if ((base != EMIF1_BASE) || !is_dra76x()) @@ -362,22 +362,22 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); /* Set region1 memory with 0 */ - rgn = ((regs->emif_ecc_address_range_1 & - EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + - CONFIG_SYS_SDRAM_BASE; + rgn_start = (regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; + rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & - EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; if (regs->emif_ecc_ctrl_reg & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) dra7_reset_ddr_data(rgn, size); /* Set region2 memory with 0 */ - rgn = ((regs->emif_ecc_address_range_2 & - EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + - CONFIG_SYS_SDRAM_BASE; + rgn_start = (regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; + rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & - EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; if (regs->emif_ecc_ctrl_reg & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) |