arm: mvebu: Add basic support for the Marvell Armada 375 SoC

This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

1 files changed, 61 insertions, 3 deletions

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 30b175c..9913802 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -54,17 +54,57 @@ int mvebu_soc_family(void)
 	case SOC_MV78260_ID:
 	case SOC_MV78460_ID:
 		return MVEBU_SOC_AXP;
+
+	case SOC_88F6720_ID:
+		return MVEBU_SOC_A375;
+
 	case SOC_88F6810_ID:
 	case SOC_88F6820_ID:
 	case SOC_88F6828_ID:
 		return MVEBU_SOC_A38X;
 	}
+
 	return MVEBU_SOC_UNKNOWN;
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375)
+/* SAR frequency values for Armada 375 */
+static const struct sar_freq_modes sar_freq_tab[] = {
+	{  0,  0x0,  266,  133,  266 },
+	{  1,  0x0,  333,  167,  167 },
+	{  2,  0x0,  333,  167,  222 },
+	{  3,  0x0,  333,  167,  333 },
+	{  4,  0x0,  400,  200,  200 },
+	{  5,  0x0,  400,  200,  267 },
+	{  6,  0x0,  400,  200,  400 },
+	{  7,  0x0,  500,  250,  250 },
+	{  8,  0x0,  500,  250,  334 },
+	{  9,  0x0,  500,  250,  500 },
+	{ 10,  0x0,  533,  267,  267 },
+	{ 11,  0x0,  533,  267,  356 },
+	{ 12,  0x0,  533,  267,  533 },
+	{ 13,  0x0,  600,  300,  300 },
+	{ 14,  0x0,  600,  300,  400 },
+	{ 15,  0x0,  600,  300,  600 },
+	{ 16,  0x0,  666,  333,  333 },
+	{ 17,  0x0,  666,  333,  444 },
+	{ 18,  0x0,  666,  333,  666 },
+	{ 19,  0x0,  800,  400,  267 },
+	{ 20,  0x0,  800,  400,  400 },
+	{ 21,  0x0,  800,  400,  534 },
+	{ 22,  0x0,  900,  450,  300 },
+	{ 23,  0x0,  900,  450,  450 },
+	{ 24,  0x0,  900,  450,  600 },
+	{ 25,  0x0, 1000,  500,  500 },
+	{ 26,  0x0, 1000,  500,  667 },
+	{ 27,  0x0, 1000,  333,  500 },
+	{ 28,  0x0,  400,  400,  400 },
+	{ 29,  0x0, 1100,  550,  550 },
+	{ 0xff, 0xff,    0,   0,   0 }	/* 0xff marks end of array */
+};
+#elif defined(CONFIG_ARMADA_38X)
 /* SAR frequency values for Armada 38x */
 static const struct sar_freq_modes sar_freq_tab[] = {
 	{  0x0,  0x0,  666, 333, 333 },
@@ -98,9 +138,13 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 	u32 freq;
 	int i;
 
+#if defined(CONFIG_ARMADA_375)
+	val = readl(CONFIG_SAR2_REG);	/* SAR - Sample At Reset */
+#else
 	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */
+#endif
 	freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
-#if !defined(CONFIG_ARMADA_38X)
+#if defined(SAR2_CPU_FREQ_MASK)
 	/*
 	 * Shift CPU0 clock frequency select bit from SAR2 register
 	 * into correct position
@@ -110,7 +154,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 #endif
 	for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
 		if (sar_freq_tab[i].val == freq) {
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
 			*sar_freq = sar_freq_tab[i];
 			return;
 #else
@@ -152,6 +196,9 @@ int print_cpuinfo(void)
 	case SOC_MV78460_ID:
 		puts("MV78460-");
 		break;
+	case SOC_88F6720_ID:
+		puts("MV88F6720-");
+		break;
 	case SOC_88F6810_ID:
 		puts("MV88F6810-");
 		break;
@@ -180,6 +227,17 @@ int print_cpuinfo(void)
 		}
 	}
 
+	if (mvebu_soc_family() == MVEBU_SOC_A375) {
+		switch (revid) {
+		case MV_88F67XX_A0_ID:
+			puts("A0");
+			break;
+		default:
+			printf("?? (%x)", revid);
+			break;
+		}
+	}
+
 	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
 		switch (revid) {
 		case MV_88F68XX_Z1_ID: