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author | Trevor Woerner <twoerner@gmail.com> | 2020-05-06 08:02:36 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-05-15 14:47:35 -0400 |
commit | b3d9a8b1857878fd72bf5385d91585fbafe516d6 (patch) | |
tree | fd11b9f6b343aabb33247b4b3fe4ccfde1cc8a6f /arch/arm/mach-lpc32xx/lowlevel_init.S | |
parent | 0ff042d836f2a40b2104d4501111fbb340293c5c (diff) | |
download | u-boot-b3d9a8b1857878fd72bf5385d91585fbafe516d6.zip u-boot-b3d9a8b1857878fd72bf5385d91585fbafe516d6.tar.gz u-boot-b3d9a8b1857878fd72bf5385d91585fbafe516d6.tar.bz2 |
arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.
Following the checklist from
commit 01f14456306c ("ARM: prepare for moving SoC sources into mach-*"):
[1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
[2] add machine entry to arch/arm/Makefile
[3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
[4] fix the Kconfig file path in arch/arm/Kconfig
[5] (no MAINTAINERS update)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Diffstat (limited to 'arch/arm/mach-lpc32xx/lowlevel_init.S')
-rw-r--r-- | arch/arm/mach-lpc32xx/lowlevel_init.S | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/lowlevel_init.S b/arch/arm/mach-lpc32xx/lowlevel_init.S new file mode 100644 index 0000000..d42da2b --- /dev/null +++ b/arch/arm/mach-lpc32xx/lowlevel_init.S @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * WORK Microwave work_92105 board low level init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Low level init is called from SPL to set up the clocks. + * On entry, the LPC3250 is in Direct Run mode with all clocks + * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is + * 104 MHz and PCLK is 13 MHz. + * + * This code must run from SRAM so that the clock changes do + * not prevent it from executing. + */ + +.globl lowlevel_init + +lowlevel_init: + + /* Set ARM, HCLK, PCLK dividers for normal mode */ + ldr r0, =0x0000003D + ldr r1, =0x40004040 + str r0, [r1] + + /* Start HCLK PLL for 208 MHz */ + ldr r0, =0x0001401E + ldr r1, =0x40004058 + str r0, [r1] + + /* wait for HCLK PLL to lock */ +1: + ldr r0, [r1] + ands r0, r0, #1 + beq 1b + + /* switch to normal mode */ + ldr r1, =0x40004044 + ldr r0, [r1] + orr r0, #0x00000004 + str r0, [r1] + + /* Return to U-Boot via saved link register */ + mov pc, lr |