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| author | Jan Kiszka <jan.kiszka@siemens.com> | 2020-05-18 07:57:22 +0200 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-05-19 14:41:13 +0530 |
| commit | c02712a7484918648e5dd09c092035c7eeb7794a (patch) | |
| tree | c039b0a9f623eefc534fb3dbffceacee041d61a7 /arch/arm/mach-k3/common.c | |
| parent | 6cfd09d4ed43ee401cc16f1dffabe7911b603380 (diff) | |
| download | u-boot-c02712a7484918648e5dd09c092035c7eeb7794a.zip u-boot-c02712a7484918648e5dd09c092035c7eeb7794a.tar.gz u-boot-c02712a7484918648e5dd09c092035c7eeb7794a.tar.bz2 | |
arm: mach-k3: Enable dcache in SPL
Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.
Based on original patch by Lokesh Vulta.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-k3/common.c')
| -rw-r--r-- | arch/arm/mach-k3/common.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 80dfa5f..a94e054 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) } } } + +void spl_enable_dcache(void) +{ +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + + dram_init_banksize(); + + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + + ram_top += get_effective_memsize(); + /* keep ram_top in the 32-bit address space */ + if (ram_top >= 0x100000000) + ram_top = (phys_addr_t) 0x100000000; + + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + dcache_enable(); +#endif +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); +} +#endif |