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| author | Anatolij Gustschin <agust@denx.de> | 2017-08-28 17:46:32 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2017-08-29 09:47:28 +0200 |
| commit | ae64226dbec2a50a2d88027018c9bd25b20c4ae0 (patch) | |
| tree | 887f0d89f68d5214418fedc29135c5d6a94afdc4 /arch/arm/mach-imx/timer.c | |
| parent | cb40adff8fd5335c0f623562c57bf8505c32b16f (diff) | |
| download | u-boot-ae64226dbec2a50a2d88027018c9bd25b20c4ae0.zip u-boot-ae64226dbec2a50a2d88027018c9bd25b20c4ae0.tar.gz u-boot-ae64226dbec2a50a2d88027018c9bd25b20c4ae0.tar.bz2 | |
imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/mach-imx/timer.c')
| -rw-r--r-- | arch/arm/mach-imx/timer.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 9b01114..69dbf3c 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -74,8 +74,7 @@ int timer_init(void) __raw_writel(GPTCR_SWR, &cur_gpt->control); /* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); + __raw_writel(0, &cur_gpt->control); i = __raw_readl(&cur_gpt->control); i &= ~GPTCR_CLKSOURCE_MASK; |