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| author | Tom Rini <trini@konsulko.com> | 2022-09-19 13:19:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-19 16:07:12 -0400 |
| commit | e9a1ff9724348408144c7f1c5b5cc26130ba46e5 (patch) | |
| tree | 68b56f117206d121b4a7e567b0209c02283c98e6 /arch/arm/include | |
| parent | b6c50e5831f6ce3800d4b3cf3c7aa35dde8c48d9 (diff) | |
| parent | f76f3e3b44328fe6229650540109af93750fd5f0 (diff) | |
| download | u-boot-e9a1ff9724348408144c7f1c5b5cc26130ba46e5.zip u-boot-e9a1ff9724348408144c7f1c5b5cc26130ba46e5.tar.gz u-boot-e9a1ff9724348408144c7f1c5b5cc26130ba46e5.tar.bz2 | |
Merge branch 'master' into next
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-imx/cpu.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/pl310.h | 9 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index d54e6e6..a666271 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f69e9e4..9d4cd68 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -7,13 +7,12 @@ #ifndef _PL310_H_ #define _PL310_H_ -#include <linux/types.h> - /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L2X0_CTRL_OFF 0x100 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) @@ -27,6 +26,10 @@ #define L2X0_CACHE_ID_RTL_MASK 0x3f #define L2X0_CACHE_ID_RTL_R3P2 0x8 +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; @@ -87,3 +90,5 @@ void pl310_inval_range(u32 start, u32 end); void pl310_clean_inval_range(u32 start, u32 end); #endif + +#endif |