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| author | Tom Rini <trini@konsulko.com> | 2022-07-23 13:05:09 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 16:18:48 -0400 |
| commit | 923a855509c6114b044b6358c98f1857f52ab80b (patch) | |
| tree | 91b5b089f9fe005a1356f63f432ef548bb89a873 /arch/arm/include | |
| parent | 6f6b9703d0149b784cce81996773e4b84323c7e1 (diff) | |
| download | u-boot-923a855509c6114b044b6358c98f1857f52ab80b.zip u-boot-923a855509c6114b044b6358c98f1857f52ab80b.tar.gz u-boot-923a855509c6114b044b6358c98f1857f52ab80b.tar.bz2 | |
Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_CCSR_GUR_BE
CONFIG_SYS_FSL_CCSR_SCFG_BE
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_IFC_BE
CONFIG_SYS_FSL_PEX_LUT_BE
CONFIG_SYS_FSL_CCSR_GUR_LE
CONFIG_SYS_FSL_CCSR_SCFG_LE
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_IFC_LE
CONFIG_SYS_FSL_PEX_LUT_LE
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 34 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 2 |
2 files changed, 0 insertions, 36 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 9aee971..f6710d0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -40,12 +40,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* Generic Interrupt Controller Definitions */ @@ -56,7 +50,6 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 @@ -141,16 +134,9 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ @@ -179,11 +165,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* Generic Interrupt Controller Definitions */ @@ -194,7 +175,6 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -234,18 +214,12 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ @@ -255,12 +229,8 @@ #define DCSR_DCFG_SBEESR2 0x20140534 #define DCSR_DCFG_MBEESR2 0x20140544 -#define CONFIG_SYS_FSL_CCSR_SCFG_BE -#define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_CCSR_GUR_BE -#define CONFIG_SYS_FSL_PEX_LUT_BE /* SoC related */ #ifdef CONFIG_ARCH_LS1043A @@ -275,8 +245,6 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_IFC_BE - /* SMMU Defintions */ #define SMMU_BASE 0x09000000 @@ -323,8 +291,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_IFC_BE - /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e5f61ea..868456f 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,8 +79,6 @@ #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif -#define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE |