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| author | Tom Rini <trini@konsulko.com> | 2022-07-23 13:05:10 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 16:18:48 -0400 |
| commit | 612f7a61d59cc71daa6296f8c2c7346b8e811caa (patch) | |
| tree | b0542bc9d5c046515f92fe12cac42e73f1e311a6 /arch/arm/include | |
| parent | 923a855509c6114b044b6358c98f1857f52ab80b (diff) | |
| download | u-boot-612f7a61d59cc71daa6296f8c2c7346b8e811caa.zip u-boot-612f7a61d59cc71daa6296f8c2c7346b8e811caa.tar.gz u-boot-612f7a61d59cc71daa6296f8c2c7346b8e811caa.tar.bz2 | |
Convert CONFIG_FSL_MEMAC et al to Kconfig
This converts the following to Kconfig:
CONFIG_FSL_MEMAC
CONFIG_SYS_MEMAC_LITTLE_ENDIAN
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index f6710d0..76e07f3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -40,8 +40,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 @@ -49,8 +47,6 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* DCFG - GUR */ - /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180 @@ -134,8 +130,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* DCFG - GUR */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -165,8 +159,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06200000 @@ -214,8 +206,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |