imx8ulp: clock: Support LPAV clocks in cgc and pcc

Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

2 files changed, 93 insertions, 5 deletions

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index 34a15fb..745fd7f 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -6,11 +6,15 @@
 #ifndef _ASM_ARCH_CGC_H
 #define _ASM_ARCH_CGC_H
 
-enum cgc1_clk {
+enum cgc_clk {
 	DUMMY0_CLK,
 	DUMMY1_CLK,
 	LPOSC,
+	NIC_APCLK,
+	NIC_PERCLK,
+	XBAR_APCLK,
 	XBAR_BUSCLK,
+	AD_SLOWCLK,
 	SOSC,
 	SOSC_DIV1,
 	SOSC_DIV2,
@@ -34,6 +38,24 @@ enum cgc1_clk {
 	PLL3_PFD2_DIV2,
 	PLL3_PFD3_DIV1,
 	PLL3_PFD3_DIV2,
+	LVDS,
+	LPAV_AXICLK,
+	LPAV_AHBCLK,
+	LPAV_BUSCLK,
+	PLL4,
+	PLL4_VCODIV,
+	PLL4_PFD0,
+	PLL4_PFD1,
+	PLL4_PFD2,
+	PLL4_PFD3,
+	PLL4_PFD0_DIV1,
+	PLL4_PFD0_DIV2,
+	PLL4_PFD1_DIV1,
+	PLL4_PFD1_DIV2,
+	PLL4_PFD2_DIV1,
+	PLL4_PFD2_DIV2,
+	PLL4_PFD3_DIV1,
+	PLL4_PFD3_DIV2,
 };
 
 struct cgc1_regs {
@@ -119,12 +141,16 @@ struct cgc2_regs {
 	u32 lvdscfg;
 };
 
-u32 cgc1_clk_get_rate(enum cgc1_clk clk);
+u32 cgc_clk_get_rate(enum cgc_clk clk);
 void cgc1_pll3_init(void);
 void cgc1_pll2_init(void);
 void cgc1_soscdiv_init(void);
 void cgc1_init_core_clk(void);
 void cgc2_pll4_init(void);
 void cgc2_ddrclk_config(u32 src, u32 div);
-u32 cgc1_sosc_div(enum cgc1_clk clk);
+u32 cgc1_sosc_div(enum cgc_clk clk);
+void cgc1_enet_stamp_sel(u32 clk_src);
+void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);
+void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div);
+void cgc2_lpav_init(enum cgc_clk clk);
 #endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 091d017..4680154 100644
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -90,6 +90,68 @@ enum pcc4_entry {
 	RGPIOF_PCC4_SLOT = 31,
 };
 
+enum pcc5_entry {
+	DMA2_MP_PCC5_SLOT = 0,
+	DMA2_CH0_PCC5_SLOT = 1,
+	DMA2_CH1_PCC5_SLOT = 2,
+	DMA2_CH2_PCC5_SLOT = 3,
+	DMA2_CH3_PCC5_SLOT = 4,
+	DMA2_CH4_PCC5_SLOT = 5,
+	DMA2_CH5_PCC5_SLOT = 6,
+	DMA2_CH6_PCC5_SLOT = 7,
+	DMA2_CH7_PCC5_SLOT = 8,
+	DMA2_CH8_PCC5_SLOT = 9,
+	DMA2_CH9_PCC5_SLOT = 10,
+	DMA2_CH10_PCC5_SLOT = 11,
+	DMA2_CH11_PCC5_SLOT = 12,
+	DMA2_CH12_PCC5_SLOT = 13,
+	DMA2_CH13_PCC5_SLOT = 14,
+	DMA2_CH14_PCC5_SLOT = 15,
+	DMA2_CH15_PCC5_SLOT = 16,
+	DMA2_CH16_PCC5_SLOT = 17,
+	DMA2_CH17_PCC5_SLOT = 18,
+	DMA2_CH18_PCC5_SLOT = 19,
+	DMA2_CH19_PCC5_SLOT = 20,
+	DMA2_CH20_PCC5_SLOT = 21,
+	DMA2_CH21_PCC5_SLOT = 22,
+	DMA2_CH22_PCC5_SLOT = 23,
+	DMA2_CH23_PCC5_SLOT = 24,
+	DMA2_CH24_PCC5_SLOT = 25,
+	DMA2_CH25_PCC5_SLOT = 26,
+	DMA2_CH26_PCC5_SLOT = 27,
+	DMA2_CH27_PCC5_SLOT = 28,
+	DMA2_CH28_PCC5_SLOT = 29,
+	DMA2_CH29_PCC5_SLOT = 30,
+	DMA2_CH30_PCC5_SLOT = 31,
+	DMA2_CH31_PCC5_SLOT = 32,
+	MU2_B_PCC5_SLOT = 33,
+	MU3_B_PCC5_SLOT = 34,
+	SEMA42_2_PCC5_SLOT = 35,
+	CMC2_PCC5_SLOT = 36,
+	AVD_SIM_PCC5_SLOT = 37,
+	LPAV_CGC_PCC5_SLOT = 38,
+	PCC5_PCC5_SLOT = 39,
+	TPM8_PCC5_SLOT = 40,
+	SAI6_PCC5_SLOT = 41,
+	SAI7_PCC5_SLOT = 42,
+	SPDIF_PCC5_SLOT = 43,
+	ISI_PCC5_SLOT = 44,
+	CSI_REGS_PCC5_SLOT = 45,
+	CSI_PCC5_SLOT = 47,
+	DSI_PCC5_SLOT = 48,
+	WDOG5_PCC5_SLOT = 50,
+	EPDC_PCC5_SLOT = 51,
+	PXP_PCC5_SLOT = 52,
+	SFA2_PCC5_SLOT = 53,
+	GPU2D_PCC5_SLOT = 60,
+	GPU3D_PCC5_SLOT = 61,
+	DCNANO_PCC5_SLOT = 62,
+	LPDDR4_PCC5_SLOT = 66,
+	CSI_CLK_UI_PCC5_SLOT = 67,
+	CSI_CLK_ESC_PCC5_SLOT = 68,
+	RGPIOD_PCC5_SLOT = 69,
+};
+
 /* PCC registers */
 #define PCC_PR_OFFSET	31
 #define PCC_PR_MASK		(0x1 << PCC_PR_OFFSET)
@@ -130,10 +192,10 @@ struct pcc_entry {
 };
 
 int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
-int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src);
+int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src);
 int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
 bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
-int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src);
+int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src);
 int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
 u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
 #endif