diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2019-07-15 02:27:06 +0100 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:09:31 +0530 |
| commit | 770b85a4180e5173c57c3297a4e28647e041f63a (patch) | |
| tree | 36288a5cd66bae0123a31c85311a3414061cd83a /arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | |
| parent | 65f80f58049a820e7d1ed7b0b0d233885ce6ebb2 (diff) | |
| download | u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.zip u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.tar.gz u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.tar.bz2 | |
sunxi: H6: move LPDDR3 timing definition into separate file
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index eeb4da5..54c4755 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -287,6 +287,31 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); #define DCR_DDR4 (4 << 0) #define DCR_DDR8BANK BIT(3) +/* + * The delay parameters allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ +#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) +/* + * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, + * Termination and Power down + */ +#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) +struct dram_para { + u32 clk; + enum sunxi_dram_type type; + u8 cols; + u8 rows; + u8 ranks; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + + static inline int ns_to_t(int nanoseconds) { const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; @@ -294,4 +319,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } +void mctl_set_timing_params(struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN50I_H6_H */ |